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| cortina systems ? ixf1104 4-port gigabit ethernet media access controller datasheet the cortina systems ? cortina systems ? ixf1104 4-port gigabit ethernet media access controller (ixf1104 mac) supports ieee 802.3* 10/100/1000 mbps applications. the ixf1104 mac supports a system packet interface phase 3 (spi3) system interface to a network processor or asic, and concurrently supports copper and fiber physical layer devices (phys). the copper phy interface supports the standard and reduced pin-count gigabit media independent interface (gmii and rgmii) for high-port-count applications. for fiber applications the integrated serializer/deseria lizer (serdes) on each port supports direct connection to optical modules to reduce pcb area requirements and system cost. product features ? four independent ethernet mac ports for copper or fiber physical layer connectivity. ? ieee 802.3 compliant ? independent enable/disable of any port ? copper mode: ? rgmii for 10/100/1000 mbps links ? gmii for 1000 mbps full-duplex links ? ieee 802.3 mdio interface ? fiber mode: ? integrated serdes interface for direct connection to 1000base-x optical modules ? ieee 802.3 auto-negotiation or forced mode ? supports sfp msa-compatible transceivers ? spi3 interface supports data transfers up to 4 gbps in both modes: ? 32-bit multi-phy mode (133 mhz) ? 4 x 8-bit single-phy mode (125 mhz) ? ieee 802.3-compliant flow control ? loss-less up to 9.6 kb packets and 5 km links ? jumbo frame support for 9.6 kb packets ? internal per-channel fifos: 32 kb rx, 10 kb tx ? flexible 32/16/8-bit cpu interface ? programmable packet handling ? filter broadcast, multicast, unicast, vlan and errored packets ? automatically pad undersized tx packets ? remove crc from rx packets ? performance monitoring and diagnostics ? rmon statistics ? crc calculation and error detection ? detection of length error, runt, or overly large packets ? counters for dropped and errored packets ? loopback modes ? jtag boundary scan ? .18 m cmos process technology ? 1.8 v core, 2.5 v rgmii, gmii, omi, and 3.3 v spi3 and cpu ? operating temperature ranges: ? copper mode:-40c to +85c ? fiber mode:0c to +70c ? package options: ? 552-ball ceramic bga (standard) ? 552-ball ceramic bga (rohs- compliant) ? 552-ball plastic fc-bga (contact your cortina sales representative)
page 2 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 legal disclaime r this document contains information proprietary to cortina syst ems, inc. any use or disclosure, in whole or in part, of this information to any unauthorized party, for any purposes other than that for which it is provided is expressly prohibited except as authorized by cortina systems, inc. in writing. cortina systems, inc. reserves its rights to pursue both civil and criminal penalties for copying or di sclosure of this material without authorization. *other names and brands may be clai med as the property of others. ? cortina systems, inc. 2006 applications ? load balancing systems ? multiservice switches ? web caching appliances ? intelligent backplane interfaces ? edge routers ? redundant line cards ? base station controllers and transceivers ? serving gprs support nodes (sgsn) ? gateway gprs support nodes (ggsn) ? packet data serving nodes (pdsn) ? dsl access multiplexers (dslam) ? cable modem termination systems (cmts) page 3 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 revision history revision number: 10.0 revision date: 28 november 2006 page # description n/a first release of this document from cortina systems, inc. revision number: 009 revision date: 27-oct-2005 page # description page 71 modified figure 8, ethernet frame format [changed preamble byte count to 7 bytes]. page 133 section 45, rgmii power [changed v cc to v dd in i ih and i il ] page 111 added bullet to section 5.7.3, i2c module configuration interface : the i2c interface only supports random single-byte reads and does not guarantee coherency when reading two-byte registers. page 219 replaced figure 56, fc-pbga package (top and bottom views) , on page 219 . page 225 modified table 182, spi3 receive configuration ($0x701) . page 238 modified table 206, optical module control ports 0 - 3 ($0x79a) : changed default values. page 239 modified table 207, i 2 c control ports 0 - 3 ($0x79b) . page 227 modified table 213, i2c data ports 0 - 9 ($0x79f) (changed address from $0x79c to $0x79f). page 220 added section 9.3.3, top label marking example . page 235 modified table 157, product information and figure 60, ordering information ? sample under section 10.0, product ordering information . page 1 added 552-ball flip chip-pbga (fc-pbga) and product ordering number information. page 222 added fc-pbga ordering number under table 157, product information . revision number: 008 revision date: august 1, 2005 (sheet 1 of 2) page # description page 1 added 552-ball ceramic ball grid array (cbga) compliant with rohs and product ordering number information. page 1 added 552-ball flip chip-pbga (fc-pbga) and product ordering number information. page 58 modified table 12, jtag interface signal descriptions : changed standard to 3.3 v lvttl from 2.5 v cmos. page 72 modified figure 9, pause frame format [changed preamble byte count to 7 bytes]. page 84 modified figure 11, mphy transmit logical timing [updated tdat[31:0]]. page 85 modified figure 12, mphy receive logical timing [updated rdat[31:0]]. page 87 modified figure 14, sphy transmit logical timing [updated tdat[7:0]]. page 88 modified figure 15, sphy receive logical timing [updated rdat[7:0] and rprty]. page 123 modified figure 35, read timing diagram - asynchronous interface : changed upx_add[12:0] to upx_add[10:0]. page 126 added paragraphs two and three under section 5.11, loopback modes . page 4 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 page 130 changed 3.3 v cmos to 2.5 v cmos under section 5.12.5, jtag clock , on page 130 . page 128 added section 6.2, disable and enable port sequences . page 133 modified table 45, rgmii power [changed v oh , v ol , v ih , v il minimum conditions to v dd and changed v in value to v dd + .3]. page 134 modified table 46, spi3 receive interface signal parameters [changed rfclk duty cycle to 45 min and 55 max; changed min for rfclk frequency to 90]. page 136 modified table 47, spi3 transmit interface signal parameters [changed tfclk duty cycle to 45 min and 55 max]. page 141 changed mdc to mdio output delay max for t3 for 2.5 mhz from 200 to 300 in table 52, mdio timing parameters , on page 141 . page 167 modified table 90, tx config word ($ port_index + 0x17) [changed default value for the register from ?0x0001a0? to ?0x000001a0? and changed default value for bit 6 (half duplex) from 1 to 0]. page 179 modified table 96, phy control ($ port index + 0x60) [added ?need one-sentence descriptions of register? and register default value]. page 180 modified table 97, phy status ($ port index + 0x61) [added ?need one-sentence descriptions of register? and register default value]. page 181 modified table 98, phy identification 1 ($ port index + 0x62) [added ?need one-sentence descriptions of register? and register default value]. page 182 modified table 99, phy identification 2 ($ port index + 0x63) [added ?need one-sentence descriptions of register? and register default value]. page 182 modified table 100, auto-negotiation advertisement ($ port index + 0x64) [added ?need one- sentence descriptions of regist er? and register default value]. page 183 modified table 101, auto-negotiation link partner base page ability ($ port index + 0x65) [added ?need one-sentence descriptions of register? and register default value]. page 184 modified table 102, auto-negotiation expansion ($ port index + 0x66) [added ?need one- sentence descriptions of regist er? and register default value]. page 185 modified table 103, auto-negotiation next page transmit ($ port index + 0x67) [added ?need one-sentence descriptions of regist er? and register default value]. page 221 modified table 178, mdio single read and write data ($0x681) [changed mdio write data to ?mdio write data to external device?]. page 223 modified table 181, spi3 transmit and global configuration ($0x700) [changed default value for bits 3:0 from ?0? to ?1? and changed default value for entire register from ?0x0020000f? to ?0x00200000?]. page 225 modified table 182, spi3 receive configuration ($0x701) [changed default value for bits 11:8 from ?0xf? to ?0x1?]. page 238 modified table 206, optical module control ports 0 - 3 ($0x79a) [changed default value for bits 16:13 from ?0xf? to ?0x1?]. page 219 added figure 56, fc-pbga package (top and bottom views) , on page 219 and figure 57, fc-pbga mechanical specifications , on page 220 . page 221 replaced figure 58, package marking example ? cortina systems marking . 229 added section 9.4, ?rohs compliance? on page 229 . page 222 added cbga rohs-compliant and fc- pbga ordering information under table 157, product information . page 222 added fc-pbga ordering number under table 157, product information . revision number: 008 revision date: august 1, 2005 (sheet 2 of 2) page # description page 5 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 revision number: 007 revision date: march 24, 2004 (sheet 1 of 5) page # description all globally replaced gbic wi th optical module interface. all globally edited signal names. all globally changed serdes and pll analog power ball names as follows: txavtt and rxavtt changed to avdd1p8_2 txav25 and rxav25 changed to avdd2p5_2 pll1_vdda and pll2_vdda changed to avdd1p8_1 pll3_vdda changed to avdd2p5_1 pll1_gnda, pll2_gnda, and pll3_gnda changed to gnd 1 reworded and rearranged the product features section on page one changed jumbo frame support from ?10 kbytes? to ?9.6 kb?. 21 changed heading to section 2.0, ?general description? [was section 2.0, ?block diagram?]. 23 / 37 reversed sections as follows: section 3.0, ?ball assignments and ball list tables? section 4.0, ?ball assignments and signal descriptions? 24 modified table 1 ?ball list in alphanumeric order by signal name? : changed a10 from vcc to vdd changed c12 from vcc to vdd changed d11 from vcc to vdd changed j20 from gnd to vdd changed ball a1 from nc to no pad. changed balls a2, a3, a22, a23, a24, b1, b2, b23, b24, c1, c24, ab1, ab24, ac1, ac2, ac23, ac24, ad1, ad2, ad3, ad22, ad23, ad24 from nc to no ball. 30 modified table 2 ?ball list in alphanumeric order by ball location? changed a10 from vcc to vdd changed c12 form vcc to vdd changed d11 from vcc to vdd changed j20 from gnd to vdd changed ball a1 from nc to no pad. changed balls a2, a3, a22, a23, a24, b1, b2, b23, b24, c1, c24, ab1, ab24, ac1, ac2, ac23, ac24, ad1, ad2, ad3, ad22, ad23, ad24 from nc to no ball. 38 updated figure 4 ?interface signals? [modified spi3 interface signals and added mphy and sphy categories; modified signal names]. 39 broke old table 1, ?ixf1104 signal descriptions? into the following: table 3 ?spi3 interface signal descriptions? on page 39 through table 14 ?power supply signal descriptions? on page 56 39 modified table 3 ?spi3 interface signal descriptions? on page 39 [edited description for dtpa; added text to tfclk description; added text to rfclk description]. 50 modified table 6 ?rgmii interface signal descriptions? [added ball designators; added notes under descriptions]. 51 modified table 7 ?cpu interface signal descriptions? [upx_data[16]: deleted j10, added m10]. 53 modified table 9 ?optical module inte rface signal descriptions? [added ball designators]. 54 modified table 10 ?mdio interface signal descriptions? [moved note from mdc to mdio]. 56 modified table 14 ?power supply signal descriptions? [added ball designators a4, a21, and ad21 to gnd; added avdd1p8_1, avdd1p8_2, avdd2p5_1, and avdd2p5_2]. page 6 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 39 modified section 4.3, ?signal description tables? [changed heading from ?signal naming conventions; added new headings section 4.1.1, ?signal name conventions? and section 4.1.2, ?register address conventions? ; and added/enhanced material under headings. 58 added new section 4.5, ?multipl exed ball connections? with table 16 ?line side interface multiplexed balls? and table 17 ?spi3 mphy/sphy interface? . 63 modified section 4.7, ?power supply sequencing? [changed language under this section and added section 4.7.1, ?power-up sequence? and section 4.7.2, ?power-down sequence? ]. 63 modified table 5 ?power supply sequencing? [deleted 3.3 v supplies stable; changed apply 1.8 v to vdd, avdd1p8_1, and avdd1p8_2; changed apply 2.5 v to avdd2p5_1 and avdd2p5_2]. 61 modified table 18 ?definition of output and bi-directional balls during hardware reset? [changed comments for optical modules]. 64 modified table 20 ?pull-up/pull-down and unused ball guidelines? [changed trst_l to pull- down; added mdio, upx_rdy_l, i 2 c_data_3:0, and tx_disable_3:0]. 64 added new section 4.9, ?analog power filtering? [including figure 6 ?analog power supply filter network? on page 65 and table 21 ?analog power balls? on page 65 ]. 66 modified/edited text under section 5.1, ?media access controller (mac)? [rearranged and created new bullets]. 67 modified first paragraph under section 5.1.1.1, ?padding of undersized frames on transmit? . 67 modified entire section 5.1.1.3, ?filtering of receive packets? . 68 added new section 5.1.1.3.6, ?filter crc error packets? . 69 added note under table 22 ?crc errored packets drop enable behavior? . 69 added new section 5.1.2, ?flow control? including figure 7 ?packet buffering fifo? , figure 8 ?ethernet frame format? , and figure 9 ?pause frame format? . 73 replaced section 5.1.2.1.5, ?transmit pause control interface? [added table 23 ?valid decodes for txpauseadd[2:0]? and modified table 10 ?transmit pause control interface? . 74 modified figure 10 ?transmit pause control interface? 75 added note under section 5.1.3.1, ?configuration? . 76 added table note to table 24 ?operational mode configuration registers? . 77 added note under section 5.1.4.3, ?fiber forced mode? . 79 modified section 5.1.6.2, ?tx statistics? [added text to third sentence in first paragraph]. 79 modified section 5.1.6.3, ?loss-less flow control? [changed ?two kilometers? to ?five kilometers? in last sentence. 80 modified section 5.1.7.1.2, ?rx fifo? [changed 10 kb to 9.6 kb; added text to last paragraph]. 83 rewrote/replaced section 5.2, ?spi3 interface? . 86 edited signal names in figure 13 ?mphy 32-bit interface? . 90 edited signal names in figure 16 ?sphy connection for two ixf1104 mac ports (8-bit interface)? . 91 added new section 5.2.2.9, ?spi3 flow control? . [removed old ?packet-level and by te-level transfers? section.} 94 modified figure 17 ?mac gmii interconnect? [edited signal names]. na removed old section 5.3.3 electrical require ments and table 27 ?electrical requirements? ? changed input high current max from 40 to 15 and input low current min from -600 to -15. 96 added a note under section 5.4, ?reduced gigabit media independent interface (rgmii)? . revision number: 007 revision date: march 24, 2004 (sheet 2 of 5) page # description page 7 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 96 modified figure 18 ?rgmii interface? [edited signal names]. 98 modified figure 19 ?tx_ctl behavior? [changed signal names]. 98 modified figure 20 ?rx_ctl behavior? [changed signal names]. 99 modified section 5.5, ?mdio control and interface? [changed 3.3 us to 3.3 ms in fourth paragraph, third sentence]. 103 modified/replaced all text under section 5.6, ?serdes interface? on page 103 [added table 29 ?serdes driver tx power levels? ]. na removed old section 5.6.2.4 ac/dc coupling. na removed old section 5.6.2.9 system jitter. 107 modified table 30 ?ixf1104 mac-to-sfp optical module interface connections? [edited signal names]. 107 modified/replaced text and deleted old ?figure 19. typical gbic module functional diagram? under section 5.7, ?optical module interface? ]. 108 modified second sentence under section 5.7.2.2.1, ?mod_def_0:3? . 109 modified second sentence under section 5.7.2.2.3, ?rx_los_0:3? . 109 removed third paragraph under section 5.7.2.2.7, ?rx_los_int? . 110 modified first and second paragraphs under section 5.7.3, ?i2c module configuration interface? . 111 modified section 5.7.3.3, ?i2c write operation? [edited portions of text]. 116 modified table 31 ?led interface signal descriptions? [changed 0.5 mhz to 720 hz for led_clk under signal description]. 119 modified table 35 ?led behavior (fiber mode)? [changed links under description to ?link led enable ($0x502)? ]. na removed old figure 30 ?cpu ? external and internal connections?. 123 modified table 37 ?byte swapper behavior? [edited/added new values]. 123 modified second paragraph under section 5.10, ?tap interface (jtag)? 126 modified figure 33 ?spi3 interface loopback path? . 126 added note under section 5.11.2, ?line side interface loopback? . 127 modified figure 34 ?line side interface loopback path? . 127 changed section 5.12, ?clocks? [from gbic output clock to i 2 c clock]. 129 changed section 5.12.6, ?i2c clock? [from gbic clock to i 2 c clock]. 130 added new section 6.0, ?applications? . 132 modified table 39 ?absolute maximum ratings? [changed serdes analog power to avdd1p8_2 and avdd2p5_2; changed ?pll1_vdda and pll2_vdda to avdd1p8_1; changed pll3_vdda to avdd2p5_1. 133 modified table 40 ?recommended operating conditions? [changed serdes analog power to avdd1p8_2 and avdd2p5_2; changed ?pll1_vdda and pll2_vdda to avdd1p8_1; changed pll3_vdda to avdd2p5_1. 134 modified table 42 ?serdes transmit characteristics? [included serdes power driver level information]. 142 modified table 49 ?gmii 1000base-t transmit signal parameters? (changed min values for t1 and t2. revision number: 007 revision date: march 24, 2004 (sheet 3 of 5) page # description page 8 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 143 modified table 50 ?gmii 1000base-t receive signal parameters? (changed min values for t1 and t2. 146 replaced old mdio timing diagram and table with figure 43 ?mdio write timing diagram? , figure 44 ?mdio read timing diagram? , and table 52 ?mdio timing parameters? . 156 broke up the old register map into table 59 ?mac control registers ($ port index + offset)? , table 60 ?mac rx statistics registers ($ port index + offset)? , table 61 ?mac tx statistics registers ($ port index + offset)? , table 62 ?phy autoscan registers ($ port index + offset)? , table 63 ?global status and configur ation registers ($ 0x500 - 0x50c)? , table 64 ?rx fifo registers ($ 0x580 - 0x5bf)? , table 65 ?tx fifo registers ($ 0x600 - 0x63e)? , table 66 ?mdio registers ($ 0x680 - 0x683)? , table 67 ?spi3 registers ($ 0x700 - 0x716)? , table 68 ?serdes registers ($ 0x780 - 0x798)? , and table 69 ?optical module registers ($ 0x799 - 0x79f)? . 159 edited table 63 ?global status and configur ation registers ($ 0x500 - 0x50c)? [no offset]. 159 edited table 64 ?rx fifo registers ($ 0x580 - 0x5bf)? [no offset]. 160 edited table 65 ?tx fifo registers ($ 0x600 - 0x63e)? [no offset]. 161 edited table 66 ?mdio registers ($ 0x680 - 0x683)? [no offset]. 161 edited table 67 ?spi3 registers ($ 0x700 - 0x716)? [no offset]. 162 edited table 68 ?serdes registers ($ 0x780 - 0x798)? [no offset]. 162 edited table 69 ?optical module r egisters ($ 0x799 - 0x79f)? [no offset]. 163 modified table 71 ?desired duplex ($ port_index + 0x02)? [changed 100 mbps to 1000 mbps in register description. 167 modified table 82 ?mac if mode and rgmii speed ($ port_index + 0x10)? [added text to register description.] 168 modified table 84 ?fc enable ($ port_index + 0x12)? [changed description for bits 1:0]. 169 modified table 88 ?rx config word ($ port_index + 0x16)? [edited register description text; changed description and type for bits 13:12]. 170 modified table 89 ?tx config word ($ port_index + 0x17)? [edited description and type for bits 14, 13:12. 171 modified table 90 ?diverse config write ($ port_index + 0x18)? [edited description and type for bits 18:8; changed bits 3:1 to reserved; added table note 2]. 172 renamed/modified table 91 ?rx packet filter control ($ port_index + 0x19)? [old register name - added rx to heading; added table note 2]. 174 modified table 93 ?mac rx statistics ($ port_index + 0x20 ? + 0x39)? [added note to rxpausemaccontrolreceivedcounter desc ription; edited note 3 and added note 4]. 178 modified table 94 ?mac tx statistics ($ port_index +0x40 ? +0x58)? [changed ?1526-max? to ?1523 - max frame size? for txpkts1519tomaxoctets description]. 193 modified table 113 ?rx fifo high watermark port 0 ($0x580)? , table 114 ?rx fifo high watermark port 1 ($0x581)? , table 115 ?rx fifo high watermark port 2 ($0x582)? , and table 116 ?rx fifo high watermark port 3 ($0x583)? [changed bits 11:0 description]. 195 renamed and modified table 121 ?rx fifo overflow frame drop counter ports 0 - 3 ($0x594 ? 0x597)? [old register name: rx fifo number of frames removed ports 0 to 3; renamed bit names to match register names; removed ?this register gets updated after one cycle of sw reset is applied? under description]. 196 modified table 123 ?rx fifo errored frame drop enable ($0x59f)? [renamed bit names to match register name]. revision number: 007 revision date: march 24, 2004 (sheet 4 of 5) page # description page 9 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 198 renamed/modified table 125 ?rx fifo errored frame drop counter ports 0 - 3 ($0x5a2 - 0x5a5)? on page 198 [older register name: rx fifo dropped packet counter for ports 0 to 3; renamed bit names to match register name]. 199 modified table 126 ?rx fifo spi3 loopback enable for ports 0 - 3 ($0x5b2)? [renamed heading and bit name; changed description and type for bits 7:0]. 201 renamed table 128 ?rx fifo transfer threshold port 0 ($0x5b8)? on page 201 [from ?rx fifo jumbo packet size; changed bit names and edited/added text under description]. 207 modified table 136 ?loop rx data to tx fifo (line-side loopback) ports 0 - 3 ($0x61f)? [renamed heading and bit name]. 208 modified table 138 ?tx fifo overflow frame drop counter ports 0 - 3 ($0x621 ? 0x624)? [renamed from tx fifo number of frames removed ports 3 - 0]. 209 modified table 139 ?tx fifo errored frame drop counter ports 0 - 3 ($0x625 ? 0x629)? [renamed from tx fifo number of dropped packets ports 0-3 and text under the description]. 210 modified table 141 ?tx fifo port drop enable ($0x63d)? [changed description for bits 3:0]. 211 modified table 142 ?mdio single command ($0x680)? [changed default; changed description and default for bits 9:8; changed default for bits 4:0]. 212 modified table 144 ?autoscan phy address enable ($0x682)? [added note to register description]. 213 modified table 146 ?spi3 transmit and global configuration ($0x700)? [broke out bits 19:16, 7:4, and 3:0 and changed description text]. 215 modified table 147 ?spi3 receive configuration ($0x701)? [broke out bits and modified all text adding sphy and mphy modes]. 221 modified table 152 ?clock and interface mode change enable ports 0 - 3 ($0x794)? [deleted second paragraph of the register description; renamed bits to match caption; changed text under description]. 222 added note under section 8.4.11, ?optical module register overview? . 222 modified table 153 ?optical module status ports 0-3 ($0x799)? [edited register description]. 222 modified table 154 ?optical module cont rol ports 0 - 3 ($0x79a)? [changed register description]. na removed/reserved table 190 ?tx and rx ac/dc coupling selection ($7x780)?. na deleted old figure 19, ?typical gb ic module functional diagram? under section 5.7, ?optical module interface? . na removed old section 5.1.1.5, ?pause command frames.? 180(old) removed old table 13. tx fifo mini frame size for mac and padding enable port 0 to 3 register (addr: 0x63e) and replaced with reserved. revision number: 007 revision date: march 24, 2004 (sheet 5 of 5) page # description revision number: 006 revision date: august 21, 2003 (sheet 1 of 2) page # description 19 modified table 1 ?ixf1104 signal descriptions? 53 modified section 5.1.1.1, ?padding of undersized frames on transmit? . 60 modified text for etherstatscollision in table 9 ?rmon additional statistics? . 87 modified table 17 ?ixf1104-to-optical module interface connections? page 10 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 65 modified first paragraph under section 5.3.1.2, ?clock rates? . 87 modified section 5.8.2.1, ?high-speed serial interface? . 100 modified figure 27 ?microprocessor ? exte rnal and internal connections? . 110 changed pecl to lvds under section 6.1, ?dc specifications? . 113 modified table note 4 in table 32 ?spi3 receive interface signal parameters? . 119 modified table 37 ?serdes timing parameters? . 125 modified table 40 ?microprocessor interface write cycle ac signal parameters? . 140 modified table 53 ?ipg receive and transmit time register (addr: port_index + 0x0a ? + 0x0c)? . 143 modified table 60 ?short runts threshold regi ster (addr: port_index + 0x14)? . 143 modified table 61 ?discard unknown control fram e register (addr: port_index + 0x15)? . 143 modified table 62 ?rx config word register bit definition (addr: port_index + 0x16)? . 145 modified table 64 ?diverseconfigwrite register (addr: port_index + 0x18)? . 148 modified table 67 ?rx statistics registers (addr: port_index + 0x20 ? + 0x39)? . 163 modified table 82 ?microprocessor interface register (addr: 0x508)? . 164 modified table 84 ?led flash rate register (addr: 0x50a)? . 169 modified table 93 ?rx fifo errored fram e drop enable register (addr: 0x59f)?. 170 modified table 96 ?rx fifo loopback enable for ports 0 - 3 register (addr: 0x5b2)?. 171 added table 98 ?rx fifo jumbo packet si ze 0-3 register (addr: 0x5b8 ? 0x5bb?. 172 added table 99 ?rx fifo jumbo packet size po rt 0 register bit definitions (addr: 0x5b8)?. 172 added table 100 ?rx fifo jumbo packet size port 1 register bit definitions (addr: 0x5b9)?. 172 added table 101 ?rx fifo jumbo packet size port 2 register bit defini tions (addr: 0x5ba)?. 172 added table 102 ?rx fifo jumbo packet size port 3 register bit defini tions (addr: 0x5bb)?. 178 modified table 110 ?tx fifo number of dropped packets register ports 0-3 (addr: 0x625 ? 0x629)?. 177 modified table 108 ?tx fifo port reset register (addr: 0x620)?. 177 modified table 108 ?tx fifo port reset register (addr: 0x620)?. 177 modified table 107 ?loop rx data to tx fi fo register ports 0 - 3 (addr: 0x61f)?. 179 added table 111 ?tx fifo occupancy counter for ports 0 - 3 registers (addr: 0x62d ? 0x630)?. 180 added table 112 ?tx fifo port drop enable register (addr: 0x63d)?. 181 modified table 114 ?mdi single command register (addr: 0x680)?. 186 added table 122 ?tx and rx power-down register (addr: 0x787)?. 194 replaced figure 53 ?ixf1104 example package marking?. revision number: 006 revision date: august 21, 2003 (sheet 2 of 2) page # description page 11 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 revision 005 revision date: april 30, 2003 page # description initial external release. revisions 001 through 004 revision date: april 2001 ? december 2002 page # description internal releases. page 12 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 contents 1.0 introduction........... ................ ................ ................ ................ ............. ............. ........... .................. 22 1.1 what you will find in this document ......... ....................................................................... 22 1.2 related documents ........................................................................................................... .22 2.0 general description ......................................................................................................... ........... 23 3.0 ball assignments and ball list tables ...................................................................................... 2 5 3.1 ball assignments ............................................................................................................ .... 25 3.2 ball list tables ............................................................................................................ ....... 26 3.2.1 balls listed in alphabetic order by signal name .................................................. 26 3.2.2 balls listed in alphabetic order by ball location .................................................. 32 4.0 ball assignments and signal de scriptions............................................................................... 38 4.1 naming conventions .......................................................................................................... 38 4.1.1 signal name conventions ..................... ................................................................ 38 4.1.2 register address conventions .............................................................................. 38 4.2 interface signal groups ..................................................................................................... .38 4.3 signal description tables .. ................................................................................................. 39 4.4 ball usage summary .......................................................................................................... 58 4.5 multiplexed ball connections..............................................................................................59 4.5.1 gmii/rgmii/serdes/omi multiplexed ball connections........................................ 59 4.5.2 spi3 mphy/sphy ball connections ..................................................................... 60 4.6 ball state during reset ..................................................................................................... .62 4.7 power supply sequencing........................... ....................................................................... 63 4.7.1 power-up sequence..............................................................................................64 4.7.2 power-down sequence ......................................................................................... 64 4.8 pull-up/pull-down ball guidelines............... ....................................................................... 64 4.9 analog power filtering...................................................................................................... .. 65 5.0 functional descriptions..................................................................................................... ......... 66 5.1 media access controller (mac) .................. ....................................................................... 66 5.1.1 features for fiber and copper mode .................................................................... 67 5.1.2 flow control...........................................................................................................69 5.1.3 mixed-mode operation .......................................................................................... 74 5.1.4 fiber mode............................................................................................................. 76 5.1.5 copper mode ......................................................................................................... 77 5.1.6 jumbo packet support .......................................................................................... 78 5.1.7 packet buffer dimension s ..................................................................................... 79 5.1.8 rmon statistics support ....................................................................................... 79 5.2 spi3 interface .............................................................................................................. ....... 83 5.2.1 mphy operation.................................................................................................... 83 5.2.2 mphy logical timing ............................................................................................ 84 5.2.3 pre-pending function ............................................................................................ 92 5.3 gigabit media independent interface (gmii) ...................................................................... 92 5.3.1 gmii signal multiplexing ........................................................................................ 93 5.3.2 gmii interface signal definition ............................................................................. 93 5.4 reduced gigabit media independent interface (rgmii) ....................................................95 page 13 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.4.1 multiplexing of data and control........ .................................................................... 95 5.4.2 timing specifics..................................................................................................... 96 5.4.3 tx_er and rx_er coding ................................................................................... 96 5.4.4 10/100 mbps functionality ..................................................................................... 98 5.5 mdio control and interface ................................................................................................ 98 5.5.1 mdio address ....................................................................................................... 99 5.5.2 mdio register descriptions .................................................................................. 99 5.5.3 clear when done .................................................................................................. 99 5.5.4 mdc generation .................................................................................................... 99 5.5.5 management frames...........................................................................................100 5.5.6 single mdi command operation .........................................................................100 5.5.7 mdi state machine ..............................................................................................100 5.5.8 autoscan operation .............................................................................................102 5.6 serdes interface ............................................................................................................ ...102 5.6.1 features...............................................................................................................102 5.6.2 functional description .........................................................................................102 5.7 optical module interface...................................................................................................1 06 5.7.1 ixf1104 mac-supported optical module interface signals................................106 5.7.2 functional descriptions .......................................................................................107 5.7.3 i2c module configuratio n interface ......................................................................108 5.8 led interface............................................................................................................... .....113 5.8.1 modes of operation .............................................................................................114 5.8.2 led interface signal description ....... ..................................................................114 5.8.3 mode 0: detailed operation .................................................................................114 5.8.4 mode 1: detailed operation .................................................................................115 5.8.5 power-on, reset, initialization .......... ..................................................................116 5.8.6 led data decodes ............................................................................................116 5.9 cpu interface ............................................................................................................... ....118 5.9.1 functional description .........................................................................................119 5.9.2 endian..................................................................................................................12 0 5.10 tap interface (jtag) ....................................................................................................... 121 5.10.1 tap state machine ..............................................................................................121 5.10.2 instruction register and supported inst ructions ..................................................122 5.10.3 id register ...........................................................................................................122 5.10.4 boundary scan register .................... ..................................................................122 5.10.5 bypass register...................................................................................................122 5.11 loopback modes ............................................................................................................. .122 5.11.1 spi3 interface loopback .....................................................................................123 5.11.2 line side interface loopback ..............................................................................123 5.12 clocks ..................................................................................................................... ..........124 5.12.1 system interface reference clocks....... ..............................................................124 5.12.2 spi3 receive and transmit clocks .......... ...........................................................125 5.12.3 rgmii clocks.......................................................................................................125 5.12.4 mdc clock...........................................................................................................125 5.12.5 jtag clock..........................................................................................................126 5.12.6 i 2 c clock..............................................................................................................126 5.12.7 led clock ............................................................................................................126 6.0 applications ................................................................................................................ ...............127 6.1 change port mode initializat ion sequence.......................................................................127 page 14 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 6.2 disable and enable port sequences ................................................................................128 6.2.1 disable port sequence ........................................................................................128 6.2.2 enable port sequence .........................................................................................128 7.0 electrical specifications ................................................................................................... ........129 7.1 dc specifications ........................................................................................................... ..130 7.1.1 undershoot / overshoot specifications ...............................................................132 7.1.2 rgmii electrical characteristics ..........................................................................132 7.2 spi3 ac timing specifications .........................................................................................133 7.2.1 receive interface timing .....................................................................................133 7.2.2 transmit interface timing ....................................................................................135 7.3 rgmii ac timing specification ........................................................................................137 7.4 gmii ac timing specification ...........................................................................................137 7.4.1 1000 base-t operation .......................................................................................137 7.5 serdes ac timing specification.......................................................................................139 7.6 mdio ac timing specification .........................................................................................139 7.6.1 mdc high-speed operation timing ......... ...........................................................140 7.6.2 mdc low-speed operation timing .....................................................................140 7.6.3 mdio ac timing..................................................................................................141 7.7 optical module and i 2 c ac timing specification..............................................................142 7.7.1 i 2 c interface timing .............................................................................................142 7.8 cpu ac timing specification ...........................................................................................143 7.8.1 cpu interface read cycle ac timing .................................................................143 7.8.2 cpu interface write cycle ac timing .................................................................144 7.9 transmit pause control ac timing specification .............................................................144 7.10 jtag ac timing specification .........................................................................................146 7.11 system ac timing specification.......................................................................................146 7.12 led ac timing specification............................................................................................147 8.0 register set................................................................................................................ ................148 8.1 document structure .......................................................................................................... 148 8.2 graphical representation ...... ...........................................................................................148 8.3 per port registers .......................................................................................................... ..149 8.4 register map ................................................................................................................ ....149 8.4.1 mac control registers ........................................................................................155 8.4.2 mac rx statistics register overview .................................................................166 8.4.3 mac tx statistics register overview..................................................................171 8.4.4 phy autoscan registers .....................................................................................174 8.4.5 global status and configuration register overview............................................180 8.4.6 rx fifo register overview ................................................................................185 8.4.7 tx fifo register overview.................................................................................195 8.4.8 mdio register overview .....................................................................................202 8.4.9 spi3 register overview.......................................................................................204 8.4.10 serdes register overview...................................................................................210 8.4.11 optical module register overview.......................................................................212 9.0 mechanical specifications ................................................................................................... .....216 9.1 overview.................................................................................................................... .......216 9.1.1 features...............................................................................................................216 9.2 package specifics ........................................................................................................... .216 9.3 package information ......................................................................................................... 217 page 15 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 9.3.1 cbga package diagrams .... ...............................................................................217 9.3.2 flip chip-plastic ball grid array package diagram .............................................218 9.3.3 top label marking example ................................................................................220 10.0 product ordering information ............................................................................................... ...222 page 16 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 figures 1 block diagram ................................................................................................................. .............. 23 2 internal architecture ......................................................................................................... ............. 24 3 552-ball cbga assignments (top view) ............... ....................................................................... 25 4 interface signals ............................................................................................................ ............... 39 5 power supply sequencing ............................... ........................................................................ ..... 64 6 analog power supply filter ne twork ............................................................................................ .65 7 packet buffering fifo ......................................................................................................... .......... 71 8 ethernet frame format ......................................................................................................... ........ 71 9 pause frame format............................................................................................................ ....... 72 10 transmit pause control interface ............................................................................................. ..... 74 11 mphy transmit logical timing ........................ ......................................................................... .... 85 12 mphy receive logical timing .................................................................................................. .... 85 13 mphy 32-bit interface ........................................................................................................ ........... 86 14 sphy transmit logical timing................................................................................................. ..... 88 15 sphy receive logical timing.................................................................................................. ..... 88 16 sphy connection for two ixf1104 mac ports (8-b it interface) .................................................. 89 17 mac gmii interconnect ........................................................................................................ ......... 93 18 rgmii interface .............................................................................................................. ............... 95 19 tx_ctl behavior .............................................................................................................. ............ 97 20 rx_ctl behavior.............................................................................................................. ............ 97 21 management frame st ructure (single-frame format) ...............................................................100 22 mdi state.................................................................................................................... .................101 23 serdes receiver jitter tolerance............................................................................................. ...105 24 i 2 c random read transaction..... ...............................................................................................11 0 25 data validity timing......................................................................................................... ............111 26 start and stop definition timing ............................................................................................. .....112 27 acknowledge timing ........................................................................................................... ........112 28 random read .................................................................................................................. ...........113 29 mode 0 timing................................................................................................................ .............115 30 mode 1 timing................................................................................................................ .............116 31 write timing diagram - asynchro nous interface .........................................................................120 32 spi3 interface loopback path ................................................................................................. ....123 33 line side interface loopback path............................................................................................ ..124 34 spi3 receive interface timing ................................................................................................ ....133 35 spi3 transmit interface timing ............................................................................................... ....135 36 rgmii interface timing ....................................................................................................... ........137 37 1000base-t transmit interface timing ......................................................................................138 38 1000base-t receive interface timing .......................................................................................138 39 serdes timing diagram ........................................................................................................ ......139 40 mdc high-speed operation timi ng ............................................................................................14 0 41 mdc low-speed operation timing........................ .....................................................................14 0 42 mdio write timing diagram .................................................................................................... ...141 43 mdio read timing diagram ..................................................................................................... ..141 44 bus timing diagram ........................................................................................................... .........142 45 write cycle diagram.......................................................................................................... ..........142 46 cpu interface read cycle ac timing.........................................................................................14 3 47 cpu interface write cycle ac timing .........................................................................................1 44 page 17 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 48 pause control interface timing ............................................................................................... ....145 49 jtag ac timing............................................................................................................... ...........146 50 system reset ac timing ....................................................................................................... .....146 51 led ac interface timing ...................................................................................................... .......147 52 memory overview diagram ...................................................................................................... ...148 53 register overview diagram.................................................................................................... .....149 54 cbga package diagram .................................. ....................................................................... ....217 55 cbga package side view diagr am ............................................................................................218 56 fc-pbga package (top and bottom views) ..............................................................................219 57 fc-pbga mechanical specifications ..........................................................................................22 0 58 package marking example ? cortina systems marking................................................................221 59 package marking example ? intel* marking ..................................................................................221 60 ordering information ? sample ................................................................................................ ...222 page 18 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 tables 1 ball list in alphanumeric order by signal name........................................................................... 26 2 ball list in alphanumeric order by ball location ........................................................................... 32 3 spi3 interface signal descriptions ................... ......................................................................... .... 40 4 serdes interface signal descriptions .......................................................................................... .. 48 5 gmii interface signal descripti ons ............................................................................................ .... 49 6 rgmii interface signal descriptions ........................................................................................... .. 51 7 cpu interface signal descriptions ............................................................................................. ... 53 8 transmit pause control interface signal descript ions .................................................................. 54 9 optical module interface signal descriptions ................................................................................ 55 10 mdio interface signal descrip tions ........................................................................................... ...56 11 led interface signal descripti ons ............................................................................................ ..... 56 12 jtag interface signal descriptions.................. ......................................................................... .... 57 13 system interface signal descriptions ......................................................................................... ... 57 14 power supply signal descriptions.................... ......................................................................... .... 57 15 ball usage summary........................................................................................................... .......... 58 16 line side interface multiplexed balls........................................................................................ ..... 59 17 spi3 mphy/sphy interface..................................................................................................... ..... 60 18 definition of output and bi-directional balls du ring hardware reset............................................ 62 19 power supply sequencing ............................... ....................................................................... ...... 64 20 pull-up/pull-down and unused ball guidelines ..... ....................................................................... 65 21 analog power balls ........................................................................................................... ............ 65 22 crc errored packets drop enable behavior...... .......................................................................... 69 23 valid decodes for txpauseadd[2: 0] ................ ................ ................ ................ ................ .......... 73 24 operational mode configuration registers ......... .......................................................................... 75 25 rmon additional statistics ................................................................................................... ........80 26 gmii interface signal definitions ............... ............................................................................. ....... 94 27 rgmii signal definitions ..................................................................................................... .......... 96 28 tx_er and rx_er coding description........................................................................................ 96 29 serdes driver tx power leve ls ................................................................................................ ..103 30 ixf1104 mac-to-sfp optical module interface connections.....................................................106 31 led interface signal descripti ons ............................................................................................ ...114 32 mode 0 clock cycle to data bit relationship ..............................................................................115 33 mode 1 clock cycle to data bit relationship ..............................................................................116 34 led_data# decodes............................................................................................................ .....117 35 led behavior (fiber mode) .......................... .......................................................................... .....117 36 led behavior (copper mode) ................................................................................................... ..118 37 byte swapper behavior ........................................................................................................ .......121 38 instruction register description.................... ......................................................................... ......122 39 absolute maximum ratings .............................. ....................................................................... ....129 40 recommended operating conditions .................... .....................................................................130 41 dc specifications ............................................................................................................ ............131 42 serdes transmit characterist ics .............................................................................................. ...131 43 serdes receive characteristics ............................................................................................... ...132 44 undershoot / overshoot limits ................................................................................................ ....132 45 rgmii power .................................................................................................................. .............133 46 spi3 receive interface signal parameters .................................................................................134 47 spi3 transmit interface signal parameters ........ ........................................................................136 page 19 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 48 rgmii interface timing parameters ............................................................................................ 137 49 gmii 1000base-t transmit signal parameters .... ................ ................ ................. ............ ........138 50 gmii 1000base-t receive signal parameters .. ................ ................ ................ ................ ........139 51 serdes timing parameters ..................................................................................................... ....139 52 mdio timing parameters ....................................................................................................... .....141 53 i 2 c ac timing characteristics .................................................................................................... .142 54 cpu interface write cycle ac signal parameters ......................................................................144 55 transmit pause control interface timing parame ters ................................................................145 56 jtag ac timing parameters .................................................................................................... ..146 57 system reset ac timing parameters ................. ........................................................................147 58 led interface ac timing parameters ................. ........................................................................14 7 59 mac control registers ($ port index + offset) ...........................................................................149 60 mac rx statistics registers ($ port index + offset)...................................................................150 61 mac tx statistics registers ($ port index + offset) ...................................................................151 62 phy autoscan registers ($ port index + offset).........................................................................152 63 global status and configuration registers ($ 0x500 - 0x50c) ...................................................152 64 rx fifo registers ($ 0x580 - 0x5bf) ........................................................................................15 2 65 tx fifo registers ($ 0x600 - 0x63e) .........................................................................................1 53 66 mdio registers ($ 0x680 - 0x683) ............................................................................................. .154 67 spi3 registers ($ 0x700 - 0x716) ............................................................................................. ..155 68 serdes registers ($ 0x780 - 0x798) ........................................................................................... 155 69 optical module registers ($ 0x799 - 0x79f) ...............................................................................155 70 station address ($ port_index +0x00 ? +0x01)...........................................................................156 71 desired duplex ($ port_index + 0x02) ............. ...........................................................................1 56 72 fd fc type ($ port_index + 0x03) ............................................................................................. 156 73 collision distance ($ port_index + 0x05) ....................................................................................1 57 74 collision threshold ($ port_index + 0x06) .......... ........................................................................15 7 75 fc tx timer value ($ port_index + 0x07) .......... ........................................................................157 76 fd fc address ($ port_index + 0x08 ? + 0x09) .........................................................................157 77 ipg receive time 1 ($ port_index + 0x0a) ........ ........................................................................158 78 ipg receive time 2 ($ port_index + 0x0b) ........ ........................................................................158 79 ipg transmit time ($ port_index + 0x0c) ..................................................................................158 80 pause threshold ($ port_index + 0x0e) .....................................................................................159 81 max frame size (addr: port_index + 0x0f) ................................................................................159 82 mac if mode and rgmii speed ($ port_index + 0x10) .............................................................160 83 flush tx ($ port_index + 0x11)............................................................................................... ....160 84 fc enable ($ port_index + 0x12) .............................................................................................. ..160 85 fc back pressure length ($ port_index + 0x13)........................................................................161 86 short runts threshold ($ port_index + 0x14) ..... ........................................................................162 87 discard unknown control frame ($ port_index + 0x15).............................................................162 88 rx config word ($ port_index + 0x16) .......................................................................................16 2 89 tx config word ($ port_index + 0x17) .......................................................................................16 3 90 diverse config write ($ port_index + 0x18) ................................................................................164 91 rx packet filter control ($ port_index + 0x19 ) ..........................................................................165 92 port multicast address ($ port_index +0x1a ? +0x1b) .......... .....................................................166 93 mac rx statistics ($ port_index + 0x20 ? + 0x 39).....................................................................167 94 mac tx statistics ($ port_index +0x40 ? +0x58) .......................................................................171 95 phy control ($ port index + 0x60) ............................................................................................ ..174 96 phy status ($ port index + 0x61) ............................................................................................. ..175 97 phy identification 1 ($ port index + 0x62) ..................................................................................1 76 page 20 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 98 phy identification 2 ($ port index + 0x63) ..................................................................................1 77 99 auto-negotiation advertisement ($ port index + 0x64) ...............................................................177 100 auto-negotiation link partner base page ability ($ port index + 0x65)......................................178 101 auto-negotiation expansion ($ port index + 0x66) .....................................................................179 102 auto-negotiation next page transmit ($ port index + 0x67) ......................................................180 103 port enable ($0x500)........................................................................................................ ...........181 104 interface mode ($0x501) ..................................................................................................... ........181 105 link led enable ($0x502).................................................................................................... .......182 106 mac soft reset ($0x505)..................................................................................................... .......182 107 mdio soft reset ($0x506) .................................................................................................... ......183 108 cpu interface ($0x508) ...................................................................................................... .........183 109 led control ($0x509) ........................................................................................................ ..........183 110 led flash rate ($0x50a)..................................................................................................... .......184 111 led fault disable ($0x50b) .................................................................................................. ......184 112 jtag id ($0x50c) ............................................................................................................ ...........185 113 rx fifo high watermark port 0 ($0x580)..................................................................................185 114 rx fifo high watermark port 1 ($0x581)..................................................................................186 115 rx fifo high watermark port 2 ($0x582)..................................................................................186 116 rx fifo high watermark port 3 ($0x583)..................................................................................186 117 rx fifo low watermark port 0 ($0x58a) ..................................................................................187 118 rx fifo low watermark port 1 ($0x58b) ..................................................................................187 119 rx fifo low watermark port 2 ($0x58c) ..................................................................................187 120 rx fifo low watermark port 3 ($0x58d) ..................................................................................188 121 rx fifo overflow frame drop counter ports 0 - 3 ($0x594 ? 0x597).......................................188 122 rx fifo port reset ($0x59e) ................................................................................................. ....188 123 rx fifo errored frame drop en able ($0x59f)..........................................................................189 124 rx fifo overflow event ($0x5a0) ............................................................................................. 190 125 rx fifo errored frame drop co unter ports 0 - 3 ($0x5a2 - 0x5a5) .........................................191 126 rx fifo spi3 loopback enable for ports 0 - 3 ($0x5b2) ..........................................................192 127 rx fifo padding and crc strip enable ($0x5b3) ....................................................................192 128 rx fifo transfer threshold port 0 ($0x5b8) .............................................................................193 129 rx fifo transfer threshold port 1 ($0x5b9) .............................................................................193 130 rx fifo transfer threshold port 2 ($0x5ba) ............................................................................194 131 rx fifo transfer threshold port 3 ($0x5bb) ............................................................................194 132 tx fifo high watermark ports 0 - 3 ($0x600 ? 0x603) .............................................................195 133 tx fifo low watermark register ports 0 - 3 ($ 0x60a ? 0x60d)...............................................196 134 tx fifo mac threshold register ports 0 - 3 ($0x614 ? 0x617) ................................................197 135 tx fifo overflow/underflow/out of sequence event ($0x61e).................................................198 136 loop rx data to tx fifo (l ine-side loopback) ports 0 - 3 ($0x61f) ......................................199 137 tx fifo port reset ($0x620)................................................................................................. .....199 138 tx fifo overflow frame drop counter ports 0 - 3 ($0x621 ? 0x624) .......................................200 139 tx fifo errored frame drop counter ports 0 - 3 ($0x625 ? 0x629) .........................................201 140 tx fifo occupancy counter for ports 0 - 3 ($0x62d ? 0x630)..................................................202 141 tx fifo port drop enable ($0x63d) ..........................................................................................2 02 142 mdio single command ($0x680) ...............................................................................................2 02 143 mdio single read and write data ($0x681) ..............................................................................203 144 autoscan phy address enable ($0x682)............... .....................................................................203 145 mdio control ($0x683) ....................................................................................................... ........204 146 spi3 transmit and global conf iguration ($0x700) ......................................................................204 147 spi3 receive configuration ($0x701) ......................................................................................... 207 page 21 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 148 address parity error packet drop counter ($0x70a) ..................................................................210 149 tx driver power level ports 0 - 3 ($0x784) ................................................................................21 0 150 tx and rx power-down ($0x787) ..............................................................................................2 10 151 rx signal detect level ports 0 - 3 ($0x793).... ...........................................................................21 1 152 clock and interface mode chan ge enable ports 0 - 3 ($0x794) .................................................211 153 optical module status ports 0-3 ($0x799)...................................................................................2 12 154 optical module control ports 0 - 3 ($0x79a) ...............................................................................21 3 155 i 2 c control ports 0 - 3 ($0x79b)................................................................................................. .214 156 i 2 c data ports 0 - 3 ($0x79f) .................................................................................................... ..214 157 product information ......................................................................................................... ............222 page 22 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 1.0 introduction this document contains information on th e ixf1104 mac, a four-port gigabit media access controller that supports ieee 802. 3 10/100/1000 mbps applications from cortina systems, inc. (cortina). 1.1 what you will find in this document this document contains the following sections: ? section 2.0, general description , on page 23 provides the block diagram system architecture. ? section 3.0, ball assignments and ball list tables , on page 25 shows the signal naming methodology and signal descriptions. ? section 4.0, ball assignments and signal descriptions , on page 38 illustrates and lists the ixf1104 ball grid diagram with two ball list tables (by signal name and ball location) ? section 5.0, functional descriptions , on page 66 gives detailed information about the operation of the ixf1104 including general features, and interface types and descriptions. ? section 7.0, electrical specifications , on page 129 provides information on the product-operating parameters, electrical specifications, and timing parameters. ? section 8.0, register set , on page 148 illustrates and lists th e memory map, detailed descriptions, default values for the register set, and detailed information on each register. ? section 9.0, mechanical specifications , on page 216 illustrates the packaging information. ? section 10.0, product ordering information , on page 222 provides ordering information. 1.2 related documents document ixf1104 media access controller design and layout guide ixf1104 media access controller thermal design considerations ixf1104 media access controller development kit manual ixf1104 media access controller specification update page 23 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 2.0 general description the ixf1104 mac provides up to a 4.0 gbps interface to four individual 10/100/ 1000 mbps full-duplex or 10/100 mbps half-duplex-capable ethernet media access controllers (macs). the network processor is supported through a system packet interface phase 3 (spi3) media interface. t he following phy interfaces are selected on a per-port basis: ? serializer/deserializer (serdes) wit h optical module interface support ? gigabit media independent interface (gmii) ? reduced gigabit media independent interface (rgmii). figure 1 illustrates the ixf1104 mac block diagram. figure 2 illustrates the ixf1104 ma c internal ar chitecture. figure 1 block diagram forwarding engine/network processor cpu ixf1104 mac serdes/rgmii/gmii interface mdio spi3 up if phy 1 device phy 2 device phy 3 device phy 4 device b3175-02 page 24 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 figure 2 internal architecture spi3 interface cpu interface rmon statistics packet tx buffer rx packet buffer packet buffer packet buffer clock control block clock register block plls mdio omi tx tx tx rx rx rx 10/100/1000 mac 10/100/1000 mac 10/100/1000 mac 10/100/1000 mac rgmii/gmii interface rgmii/gmii interface rgmii/gmii interface rgmii/gmii interface pma layer serdes pma layer serdes pma layer serdes pma layer serdes b3176-01 page 25 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 3.0 ball assignments and ball list tables 3.1 ball assignments see figure 3 , table 1, ball list in alphanumeric order by signal name , on page 26 , and table 2, ball list in alphanumeric order by ball location , on page 32 for the ixf1104 mac ball assignments. figure 3 552-ball cbga assignments (top view) b1458-01 1 ad ac ab aa y w v u t r p n m l k j h g f e d c b a ad ac ab aa y w v u t r p n m l k j h g f e d c b a 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 v7 u7 t7 r7 p7 n7 m7 l7 k7 j7 h7 g7 f7 e7 d7 g7 b7 a7 v8 v9 v10 v11 v12 v13 v14 v15 v16 v 17 v18 v19 v20 v21 v22 v23 v24 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 u21 u22 u23 u24 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 p23 p24 n8 n9 n10 n11 n12 n13 n14 n15 n16 n17 n18 n19 n20 n121 n22 n23 n24 m8 m9 m10 m11 m12 m13 m14 m15 m16 m17 m18 m19 m20 m21 m22 m23 m24 l8 l9 l10 l11 l12 l13 l14 l15 l16 l17 l18 l19 l20 l21 l22 l23 l24 k8 k9 k10 k11 k12 k13 k14 k15 k16 k17 k18 k19 k20 k21 k22 k23 k24 j8 j9 j10 j11 j12 j13 j14 j15 j16 j17 j18 j19 j20 j21 j22 j23 j24 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 h20 h21 h22 h23 h24 g8 g9 g10 g11 g12 g13 g14 g15 g16 g17 g18 g19 g20 g21 g22 g23 g24 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 f20 f21 f22 f23 f24 e8 e9 e10 e11 e12 e13 e14 e15 e16 e17 e18 e19 e20 e21 e22 e23 e24 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 c21 c22 c23 c24 b28 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 = no ball (a2, a3, a22, a23, a24, b1, b2, b23, b24, c1, c24, ab1, ab24, ac1, ac2, ac23, ac24, ad1, ad2, ad3, ad22, ad23, ad24) = no pad (a1) w24 y24 aa24 ab24 ac24 ad24 w23 y23 aa23 ab23 ac23 ad23 w22 y22 aa22 ab22 ac22 ad22 w21 y21 aa21 ab21 ac21 ad21 w20 y20 aa20 ab20 ac20 ad20 w19 y19 aa19 ab19 ac19 ad19 w18 y18 aa18 ab18 ac18 ad18 w17 y17 aa17 ab17 ac17 ad17 w16 y16 aa16 ab16 ac16 ad16 w15 y15 aa15 ab15 ac15 ad15 w14 y14 aa14 ab14 ac14 ad14 w13 y13 aa13 ab13 ac13 ad13 w12 y12 aa12 ab12 ac12 ad12 w11 y11 aa11 ab11 ac11 ad11 w10 y10 aa10 ab10 ac10 ad10 w9 y9 aa9 ab9 ac9 ad9 w8 y8 aa8 ab8 ac8 ad8 w7 y7 aa7 ab7 ac7 ad7 a6 b6 c6 d6 f6 f6 g6 h6 j6 k6 l6 m6 n6 p6 r6 t6 u6 v6 w6 y6 aa6 ab6 ac6 ad6 a5 b5 c5 d5 e5 f5 g5 h5 j5 k5 l5 m5 n5 p5 r5 t5 u5 v5 w5 y5 aa4 ab5 ac5 ad5 a4 b4 c4 d4 e4 f4 g4 h4 j4 k4 l4 m4 n4 p4 r4 t4 u4 v4 w4 y4 aa4 ab4 ac4 ad4 a3 b3 c3 d3 e3 f3 g3 h3 j3 k3 l3 m3 n3 p13 r3 t3 u3 v3 w3 y3 aa3 ab3 ac3 ad3 a2 b2 c2 d2 e2 f2 g2 h2 j2 k2 l2 m2 n2 p2 r2 t2 u2 v2 w2 y2 aa2 ab2 ad2 b1 c1 d1 e1 f1 g1 h1 j1 k1 l1 m1 n1 p1 r1 t1 u1 v1 w1 y1 aa1 ab1 ac1 ac2 a1 ad1 page 26 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 3.2 ball list tables 3.2.1 balls listed in alphab etic order by signal name table 1 shows the ball locations and signal names arranged in alphanumeric order by signal name. the following table notes relate to ta b l e 1 and ta b l e 2 : 1. gmii ball connection: see table 16 for connection in rgmii or fiber mode. 2. spi3 ball connection: see table 17 for proper sphy and mphy connection. 3. fiber mode ball connection: see table 16 for use in rgmii and gmii (copper mode). table 1 ball list in alphanum eric order by signal name signal name ball location avdd1p8_1 a5 avdd1p8_1 a20 avdd1p8_2 t23 avdd1p8_2 ab16 avdd2p5_1 ad20 avdd2p5_2 r18 avdd2p5_2 u14 clk125 ad19 col_0 1 ab6 col_1 1 ab10 col_2 1 ad15 col_3 1 ab17 crs_0 1 aa5 crs_1 1 aa9 crs_2 1 ab15 crs_3 1 ac16 dtpa_0 2 d3 dtpa_1 2 l1 dtpa_2 2 a9 dtpa_3 2 j7 gnd b6 gnd b10 gnd b15 gnd b19 gnd d4 gnd d8 gnd d12 gnd d13 gnd d17 gnd d21 gnd f2 gnd f6 gnd f10 gnd f15 gnd f19 gnd f23 gnd h4 gnd h8 gnd h12 gnd h13 gnd h17 gnd h21 gnd j10 gnd j15 gnd k2 gnd k6 gnd k9 gnd k11 gnd k14 gnd k16 gnd k19 gnd k23 signal name ball location gnd l10 gnd l12 gnd l13 gnd l15 gnd m4 gnd m8 gnd m11 gnd m14 gnd m17 gnd m21 gnd n4 gnd n8 gnd n11 gnd n14 gnd n17 gnd n21 gnd p10 gnd p12 gnd p13 gnd p15 gnd r2 gnd r6 gnd r9 gnd r11 gnd r14 gnd r16 signal name ball location page 27 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 gnd r19 gnd r23 gnd t10 gnd t15 gnd u4 gnd u8 gnd u12 gnd u13 gnd u17 gnd u21 gnd w2 gnd w6 gnd w10 gnd w15 gnd w19 gnd w23 gnd aa4 gnd aa8 gnd aa12 gnd aa13 gnd aa17 gnd aa21 gnd ac6 gnd ac10 gnd ac15 gnd ac19 gnd ac14 gnd l20 gnd l5 gnd r7 gnd ab12 gnd a4 gnd a21 gnd ad21 i 2 c_clk l23 i 2 c_data_0 3 l24 i 2 c_data_1 3 m24 i 2 c_data_2 3 n24 signal name ball location i 2 c_data_3 3 p24 led_clk k24 led_data m22 led_latch l22 mdc 4 w24 mdio 4 v21 mod_def_int n22 nc d24 nc e12 nc f11 nc g15 nc h7 nc h18 nc j21 nc k7 nc k18 nc k20 nc k22 nc l18 nc l19 nc l21 nc m7 nc m18 nc m20 nc n3 nc n18 nc p2 nc p4 nc p6 nc p7 nc p8 nc p17 nc p18 nc r5 nc r10 nc r12 nc r13 nc r15 signal name ball location nc r20 nc t6 nc t7 nc t8 nc t9 nc t21 nc t22 nc u5 nc u7 nc u9 nc u11 nc u18 nc v9 nc v10 nc v11 nc v13 nc ab18 nc ad4 nc ad5 no ball a2 no ball a3 no ball a22 no ball a23 no ball a24 no ball b1 no ball b2 no ball b23 no ball b24 no ball c1 no ball c24 no ball ab1 no ball ab24 no ball ac1 no ball ac2 no ball ac23 no ball ac24 no ball ad1 no ball ad2 signal name ball location page 28 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 no ball ad3 no ball ad22 no ball ad23 no ball ad24 no pad a1 ptpa 2 b11 rdat_0 2 a15 rdat_1 2 a14 rdat_2 2 b14 rdat_3 2 c14 rdat_4 2 c13 rdat_5 2 d14 rdat_6 2 e14 rdat_7 2 f14 rdat_8 2 a17 rdat_9 2 c17 rdat_10 2 d16 rdat_11 2 e16 rdat_12 2 f16 rdat_13 2 e17 rdat_14 2 e18 rdat_15 2 f18 rdat_16 2 b20 rdat_17 2 b22 rdat_18 2 c20 rdat_19 2 c21 rdat_20 2 c22 rdat_21 2 d22 rdat_22 2 e22 rdat_23 2 e21 rdat_24 2 g18 rdat_25 2 g19 rdat_26 2 g20 rdat_27 2 g21 rdat_28 2 g22 rdat_29 2 g23 rdat_30 2 g24 rdat_31 2 f24 signal name ball location renb_0 2 a13 renb_1 2 a18 renb_2 2 c19 renb_3 2 e24 reop_0 2 c16 reop_1 2 d18 reop_2 2 c23 reop_3 2 j19 rerr_0 2 a16 rerr_1 2 g17 rerr_2 2 d20 rerr_3 2 h20 rfclk 2 a19 rmod0 2 g14 rmod1 2 g13 rprty_0 2 e15 rprty_1 2 g16 rprty_2 2 e20 rprty_3 2 f20 rsop_0 2 b16 rsop_1 2 c18 rsop_2 2 e23 rsop_3 2 j18 rsx 2 e13 rval_0 2 c15 rval_1 2 b18 rval_2 2 e19 rval_3 2 f22 rx_dv_0 1 v5 rx_dv_1 1 ab11 rx_dv_2 1 y24 rx_dv_3 1 v18 rx_er_0 1 w5 rx_er_1 1 y12 rx_er_2 1 aa22 rx_er_3 1 u20 rx_los_int 3 p19 rx_n_0 3 r22 signal name ball location rx_n_1 3 u22 rx_n_2 3 r24 rx_n_3 3 v24 rx_p_0 3 p22 rx_p_1 3 v22 rx_p_2 3 t24 rx_p_3 3 u24 rxc_0 1 v4 rxc_1 1 ad11 rxc_2 1 aa24 rxc_3 1 v23 rxd0_0 1 v8 rxd0_1 1 y9 rxd0_2 1 y20 rxd0_3 1 y17 rxd1_0 1 v7 rxd1_1 1 y11 rxd1_2 1 y21 rxd1_3 1 y18 rxd2_0 1 w7 rxd2_1 1 w11 rxd2_2 1 y22 rxd2_3 1 y19 rxd3_0 1 y7 rxd3_1 1 w9 rxd3_2 1 y23 rxd3_3 1 w18 rxd4_0 1 y6 rxd4_1 1 ad10 rxd4_2 1 w22 rxd4_3 1 t16 rxd5_0 1 y5 rxd5_1 1 ac11 rxd5_2 1 v20 rxd5_3 1 t17 rxd6_0 1 ab5 rxd6_1 1 aa11 rxd6_2 1 v19 signal name ball location page 29 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 rxd6_3 1 t18 rxd7_0 1 ac5 rxd7_1 1 y10 rxd7_2 1 w20 rxd7_3 1 t19 stpa 2 c11 sys_rst_l ad12 tadr0 2 a11 tadr1 2 a12 tclk j22 tdat0 2 b3 tdat1 2 c2 tdat2 2 c3 tdat3 2 d1 tdat4 2 c4 tdat5 2 c5 tdat6 2 b5 tdat7 2 c6 tdat8 2 f1 tdat9 2 g1 tdat10 2 g2 tdat11 2 h1 tdat12 2 j1 tdat13 2 j2 tdat14 2 j3 tdat15 2 h3 tdat16 2 e5 tdat17 2 e6 tdat18 2 e7 tdat19 2 e8 tdat20 2 e9 tdat21 2 e10 tdat22 2 f9 tdat23 2 c8 tdat24 2 g4 tdat25 2 g5 tdat26 2 g6 tdat27 2 g7 signal name ball location tdat28 2 g8 tdat29 2 g9 tdat30 2 f5 tdat31 2 f7 tdi j24 tdo h24 tenb_0 2 b7 tenb_1 2 e2 tenb_2 2 c9 tenb_3 2 j4 teop_0 2 a7 teop_1 2 f3 teop_2 2 e4 teop_3 2 h5 terr_0 2 a8 terr_1 2 k1 terr_2 2 e11 terr_3 2 j8 tfclk 2 d7 tmod0 2 a6 tmod1 2 d9 tms h22 tprty_0 2 d5 tprty_1 2 g3 tprty_2 2 b9 tprty_3 2 j6 trst_l j23 tsop_0 2 c7 tsop_1 2 e3 tsop_2 2 c10 tsop_3 2 j5 tsx e1 tx_en_0 1 ab2 tx_en_1 1 y8 tx_en_2 1 ac22 tx_en_3 1 v12 tx_er_0 1 w1 tx_er_1 1 ad6 signal name ball location tx_er_2 1 ad17 tx_er_3 1 ab13 tx_fault_int 3 p23 tx_n_0 3 y14 tx_n_1 3 ad14 tx_n_2 3 y16 tx_n_3 3 ad18 tx_p_0 3 y13 tx_p_1 3 ad13 tx_p_2 3 w16 tx_p_3 3 ac18 txc_0 1 aa1 txc_1 1 ad7 txc_2 1 ac20 txc_3 1 ab14 txd0_0 1 y1 txd0_1 1 ac7 txd0_2 1 ab20 txd0_3 1 v14 txd1_0 1 y2 txd1_1 1 ab7 txd1_2 1 ab21 txd1_3 1 v15 txd2_0 1 y3 txd2_1 1 ab9 txd2_2 1 ab22 txd2_3 1 v16 txd3_0 1 aa3 txd3_1 1 ad9 txd3_2 1 ab23 txd3_3 1 v17 txd4_0 1 ab3 txd4_1 1 aa7 txd4_2 1 ad16 txd4_3 1 aa14 txd5_0 1 ac3 txd5_1 1 ab8 txd5_2 1 ab19 signal name ball location page 30 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 txd5_3 1 y15 txd6_0 1 ab4 txd6_1 1 ad8 txd6_2 1 aa20 txd6_3 1 aa16 txd7_0 1 y4 txd7_1 1 ac9 txd7_2 1 aa18 txd7_3 1 w14 txpause_add0 n20 txpause_add1 p20 txpause_add2 p21 txpausefr t20 upx_add0 p3 upx_add1 n1 upx_add2 p1 upx_add3 r1 upx_add4 t1 upx_add5 u1 upx_add6 v1 upx_add7 v2 upx_add8 v3 upx_add9 u3 upx_add10 t3 upx_badd0 t2 upx_badd1 w3 upx_cs_l r3 upx_data0 l2 upx_data1 k3 upx_data2 l3 upx_data3 m3 upx_data4 l4 upx_data5 n5 upx_data6 m5 upx_data7 k5 upx_data8 p5 upx_data9 l6 upx_data10 l7 signal name ball location upx_data11 n7 upx_data12 l8 upx_data13 h9 upx_data14 j9 upx_data15 n10 upx_data16 m10 upx_data17 k10 upx_data18 g10 upx_data19 h11 upx_data20 g11 upx_data21 k12 upx_data22 g12 upx_data23 k13 upx_data24 h14 upx_data25 k15 upx_data26 n15 upx_data27 m15 upx_data28 j16 upx_data29 h16 upx_data30 j17 upx_data31 l17 upx_rd_l v6 upx_rdy_l m1 upx_width0 u16 upx_width1 t5 upx_wr_l t4 vdd d6 vdd d10 vdd d15 vdd d19 vdd f4 vdd f21 vdd h10 vdd h15 vdd j11 vdd j14 vdd k4 vdd k8 signal name ball location vdd k17 vdd k21 vdd l9 vdd l11 vdd l14 vdd l16 vdd p9 vdd p11 vdd p14 vdd p16 vdd r4 vdd r8 vdd r17 vdd r21 vdd t11 vdd t14 vdd u10 vdd u15 vdd w4 vdd w21 vdd aa6 vdd aa10 vdd aa15 vdd aa19 vdd c12 vdd d11 vdd j20 vdd a10 vdd2 b4 vdd2 b8 vdd2 b12 vdd2 d2 vdd2 f8 vdd2 f12 vdd2 h2 vdd2 h6 vdd2 j12 vdd2 m2 signal name ball location page 31 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 vdd2 m6 vdd2 m9 vdd2 m12 vdd3 b13 vdd3 b17 vdd3 b21 vdd3 d23 vdd3 f13 vdd3 f17 vdd3 h19 vdd3 h23 vdd3 j13 vdd3 m13 vdd3 m16 vdd3 m19 vdd3 m23 vdd4 n13 vdd4 n16 vdd4 n19 vdd4 n23 vdd4 t13 vdd4 u19 vdd4 u23 vdd4 w13 vdd4 w17 vdd4 aa23 vdd4 ac13 vdd4 ac17 vdd4 ac21 vdd5 n2 vdd5 n6 vdd5 n9 vdd5 n12 vdd5 t12 vdd5 u2 vdd5 u6 vdd5 w8 vdd5 w12 signal name ball location vdd5 aa2 vdd5 ac4 vdd5 ac8 vdd5 ac12 signal name ball location page 32 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 3.2.2 balls listed in alphab etic order by ball location table 2 shows the ball locations and signal names arranged in order by ball location. table 2 ball list in alphanumeric order by ball location ball location signal name a1 no pad a2 no ball a3 no ball a4 gnd a5 avdd1p8_1 a6 tmod0 2 a7 teop_0 2 a8 terr_0 2 a9 dtpa_2 2 a10 vdd a11 tadr0 2 a12 tadr1 2 a13 renb_0 2 a14 rdat_1 2 a15 rdat_0 2 a16 rerr_0 2 a17 rdat_8 2 a18 renb_1 2 a19 rfclk 2 a20 avdd1p8_1 a21 gnd a22 no ball a23 no ball a24 no ball b1 no ball b2 no ball b3 tdat0 2 b4 vdd2 b5 tdat6 2 b6 gnd b7 tenb_0 2 b8 vdd2 b9 tprty_2 2 b10 gnd b11 ptpa 2 b12 vdd2 b13 vdd3 b14 rdat_2 2 b15 gnd b16 rsop_0 2 b17 vdd3 b18 rval_1 2 b19 gnd b20 rdat_16 2 b21 vdd3 b22 rdat_17 2 b23 no ball b24 no ball c1 no ball c2 tdat1 2 c3 tdat2 2 c4 tdat4 2 c5 tdat5 2 c6 tdat7 2 c7 tsop_0 2 c8 tdat23 2 c9 tenb_2 2 c10 tsop_2 2 c11 stpa 2 c12 vdd c13 rdat_4 2 c14 rdat_3 2 c15 rval_0 2 c16 reop_0 2 c17 rdat_9 2 c18 rsop_1 2 c19 renb_2 2 c20 rdat_18 2 c21 rdat_19 2 c22 rdat_20 2 ball location signal name c23 reop_2 2 c24 no ball d1 tdat3 2 d2 vdd2 d3 dtpa_0 2 d4 gnd d5 tprty_0 2 d6 vdd d7 tfclk 2 d8 gnd d9 tmod1 2 d10 vdd d11 vdd d12 gnd d13 gnd d14 rdat_5 2 d15 vdd d16 rdat_10 2 d17 gnd d18 reop_1 2 d19 vdd d20 rerr_2 2 d21 gnd d22 rdat_21 2 d23 vdd3 d24 nc e1 tsx e2 tenb_1 2 e3 tsop_1 2 e4 teop_2 2 e5 tdat16 2 e6 tdat17 2 e7 tdat18 2 e8 tdat19 2 e9 tdat20 2 ball location signal name page 33 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 e10 tdat21 2 e11 terr_2 2 e12 nc e13 rsx 2 e14 rdat_6 2 e15 rprty_0 2 e16 rdat_11 2 e17 rdat_13 2 e18 rdat_14 2 e19 rval_2 2 e20 rprty_2 2 e21 rdat_23 2 e22 rdat_22 2 e23 rsop_2 2 e24 renb_3 2 f1 tdat8 2 f2 gnd f3 teop_1 2 f4 vdd f5 tdat30 2 f6 gnd f7 tdat31 2 f8 vdd2 f9 tdat22 2 f10 gnd f11 nc f12 vdd2 f13 vdd3 f14 rdat_7 2 f15 gnd f16 rdat_12 2 f17 vdd3 f18 rdat_15 2 f19 gnd f20 rprty_3 2 f21 vdd f22 rval_3 2 f23 gnd ball location signal name f24 rdat_31 2 g1 tdat9 2 g2 tdat10 2 g3 tprty_1 2 g4 tdat24 2 g5 tdat25 2 g6 tdat26 2 g7 tdat27 2 g8 tdat28 2 g9 tdat29 2 g10 upx_data18 g11 upx_data20 g12 upx_data22 g13 rmod1 2 g14 rmod0 2 g15 nc g16 rprty_1 2 g17 rerr_1 2 g18 rdat_24 2 g19 rdat_25 2 g20 rdat_26 2 g21 rdat_27 2 g22 rdat_28 2 g23 rdat_29 2 g24 rdat_30 2 h1 tdat11 2 h2 vdd2 h3 tdat15 2 h4 gnd h5 teop_3 2 h6 vdd2 h7 nc h8 gnd h9 upx_data13 h10 vdd h11 upx_data19 h12 gnd h13 gnd ball location signal name h14 upx_data24 h15 vdd h16 upx_data29 h17 gnd h18 nc h19 vdd3 h20 rerr_3 2 h21 gnd h22 tms h23 vdd3 h24 tdo j1 tdat12 2 j2 tdat13 2 j3 tdat14 2 j4 tenb_3 2 j5 tsop_3 2 j6 tprty_3 2 j7 dtpa_3 2 j8 terr_3 2 j9 upx_data14 j10 gnd j11 vdd j12 vdd2 j13 vdd3 j14 vdd j15 gnd j16 upx_data28 j17 upx_data30 j18 rsop_3 2 j19 reop_3 2 j20 vdd j21 nc j22 tclk j23 trst_l j24 tdi k1 terr_1 2 k2 gnd k3 upx_data1 ball location signal name page 34 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 k4 vdd k5 upx_data7 k6 gnd k7 nc k8 vdd k9 gnd k10 upx_data17 k11 gnd k12 upx_data21 k13 upx_data23 k14 gnd k15 upx_data25 k16 gnd k17 vdd k18 nc k19 gnd k20 nc k21 vdd k22 nc k23 gnd k24 led_clk l1 dtpa_1 2 l2 upx_data0 l3 upx_data2 l4 upx_data4 l5 gnd l6 upx_data9 l7 upx_data10 l8 upx_data12 l9 vdd l10 gnd l11 vdd l12 gnd l13 gnd l14 vdd l15 gnd l16 vdd l17 upx_data31 ball location signal name l18 nc l19 nc l20 gnd l21 nc l22 led_latch l23 i 2 c_clk l24 i 2 c_data_0 3 m1 upx_rdy_l m2 vdd2 m3 upx_data3 m4 gnd m5 upx_data6 m6 vdd2 m7 nc m8 gnd m9 vdd2 m10 upx_data16 m11 gnd m12 vdd2 m13 vdd3 m14 gnd m15 upx_data27 m16 vdd3 m17 gnd m18 nc m19 vdd3 m20 nc m21 gnd m22 led_data m23 vdd3 m24 i 2 c_data_1 3 n1 upx_add1 n2 vdd5 n3 nc n4 gnd n5 upx_data5 n6 vdd5 n7 upx_data11 ball location signal name n8 gnd n9 vdd5 n10 upx_data15 n11 gnd n12 vdd5 n13 vdd4 n14 gnd n15 upx_data26 n16 vdd4 n17 gnd n18 nc n19 vdd4 n20 txpause_add0 n21 gnd n22 mod_def_int n23 vdd4 n24 i 2 c_data_2 3 p1 upx_add2 p2 nc p3 upx_add0 p4 nc p5 upx_data8 p6 nc p7 nc p8 nc p9 vdd p10 gnd p11 vdd p12 gnd p13 gnd p14 vdd p15 gnd p16 vdd p17 nc p18 nc p19 rx_los_int 3 p20 txpause_add1 p21 txpause_add2 ball location signal name page 35 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 p22 rx_p_0 3 p23 tx_fault_int 3 p24 i 2 c_data_3 3 r1 upx_add3 r2 gnd r3 upx_cs_l r4 vdd r5 nc r6 gnd r7 gnd r8 vdd r9 gnd r10 nc r11 gnd r12 nc r13 nc r14 gnd r15 nc r16 gnd r17 vdd r18 avdd2p5_2 r19 gnd r20 nc r21 vdd r22 rx_n_0 3 r23 gnd r24 rx_n_2 3 t1 upx_add4 t2 upx_badd0 t3 upx_add10 t4 upx_wr_l t5 upx_width1 t6 nc t7 nc t8 nc t9 nc t10 gnd t11 vdd ball location signal name t12 vdd5 t13 vdd4 t14 vdd t15 gnd t16 rxd4_3 1 t17 rxd5_3 1 t18 rxd6_3 1 t19 rxd7_3 1 t20 txpausefr t21 nc t22 nc t23 avdd1p8_2 t24 rx_p_2 3 u1 upx_add5 u2 vdd5 u3 upx_add9 u4 gnd u5 nc u6 vdd5 u7 nc u8 gnd u9 nc u10 vdd u11 nc u12 gnd u13 gnd u14 avdd2p5_2 u15 vdd u16 upx_width0 u17 gnd u18 nc u19 vdd4 u20 rx_er_3 1 u21 gnd u22 rx_n_1 3 u23 vdd4 u24 rx_p_3 3 v1 upx_add6 ball location signal name v2 upx_add7 v3 upx_add8 v4 rxc_0 1 v5 rx_dv_0 1 v6 upx_rd_l v7 rxd1_0 1 v8 rxd0_0 1 v9 nc v10 nc v11 nc v12 tx_en_3 1 v13 nc v14 txd0_3 1 v15 txd1_3 1 v16 txd2_3 1 v17 txd3_3 1 v18 rx_dv_3 1 v19 rxd6_2 1 v20 rxd5_2 1 v21 mdio 4 v22 rx_p_1 3 v23 rxc_3 1 v24 rx_n_3 3 w1 tx_er_0 1 w2 gnd w3 upx_badd1 w4 vdd w5 rx_er_0 1 w6 gnd w7 rxd2_0 1 w8 vdd5 w9 rxd3_1 1 w10 gnd w11 rxd2_1 1 w12 vdd5 w13 vdd4 w14 txd7_3 1 w15 gnd ball location signal name page 36 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 w16 tx_p_2 3 w17 vdd4 w18 rxd3_3 1 w19 gnd w20 rxd7_2 1 w21 vdd w22 rxd4_2 1 w23 gnd w24 mdc 4 y1 txd0_0 1 y2 txd1_0 1 y3 txd2_0 1 y4 txd7_0 1 y5 rxd5_0 1 y6 rxd4_0 1 y7 rxd3_0 1 y8 tx_en_1 1 y9 rxd0_1 1 y10 rxd7_1 1 y11 rxd1_1 1 y12 rx_er_1 1 y13 tx_p_0 3 y14 tx_n_0 3 y15 txd5_3 1 y16 tx_n_2 3 y17 rxd0_3 1 y18 rxd1_3 1 y19 rxd2_3 1 y20 rxd0_2 1 y21 rxd1_2 1 y22 rxd2_2 1 y23 rxd3_2 1 y24 rx_dv_2 1 aa1 txc_0 1 aa2 vdd5 aa3 txd3_0 1 aa4 gnd aa5 crs_0 1 ball location signal name aa6 vdd aa7 txd4_1 1 aa8 gnd aa9 crs_1 1 aa10 vdd aa11 rxd6_1 1 aa12 gnd aa13 gnd aa14 txd4_3 1 aa15 vdd aa16 txd6_3 1 aa17 gnd aa18 txd7_2 1 aa19 vdd aa20 txd6_2 1 aa21 gnd aa22 rx_er_2 1 aa23 vdd4 aa24 rxc_2 1 ab1 no ball ab2 tx_en_0 1 ab3 txd4_0 1 ab4 txd6_0 1 ab5 rxd6_0 1 ab6 col_0 1 ab7 txd1_1 1 ab8 txd5_1 1 ab9 txd2_1 1 ab10 col_1 1 ab11 rx_dv_1 1 ab12 gnd ab13 tx_er_3 1 ab14 txc_3 1 ab15 crs_2 1 ab16 avdd1p8_2 ab17 col_3 1 ab18 nc ab19 txd5_2 1 ball location signal name ab20 txd0_2 1 ab21 txd1_2 1 ab22 txd2_2 1 ab23 txd3_2 1 ab24 no ball ac1 no ball ac2 no ball ac3 txd5_0 1 ac4 vdd5 ac5 rxd7_0 1 ac6 gnd ac7 txd0_1 1 ac8 vdd5 ac9 txd7_1 1 ac10 gnd ac11 rxd5_1 1 ac12 vdd5 ac13 vdd4 ac14 gnd ac15 gnd ac16 crs_3 1 ac17 vdd4 ac18 tx_p_3 3 ac19 gnd ac20 txc_2 1 ac21 vdd4 ac22 tx_en_2 1 ac23 no ball ac24 no ball ad1 no ball ad2 no ball ad3 no ball ad4 nc ad5 nc ad6 tx_er_1 1 ad7 txc_1 1 ad8 txd6_1 1 ad9 txd3_1 1 ball location signal name page 37 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 ad10 rxd4_1 1 ad11 rxc_1 1 ad12 sys_rst_l ad13 tx_p_1 3 ad14 tx_n_1 3 ad15 col_2 1 ad16 txd4_2 1 ad17 tx_er_2 1 ad18 tx_n_3 3 ad19 clk125 ad20 avdd2p5_1 ad21 gnd ad22 no ball ad23 no ball ad24 no ball ball location signal name page 38 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 4.0 ball assignments and signal descriptions 4.1 naming conventions 4.1.1 signal name conventions signal names begin with a signal mnemonic, and can also contain one or more of the following designations: a differential pair de signation, a serial designation, a port designation (rgmii interface), and an active low designation. signal naming conventions are as follows: differential pair + port designation. the positive and negative components of differential pairs tied to a specific po rt are designated by the signal mnemonic, immediately followed by an underscore and ei ther p (positive component) or n (negative component), and an underscore followed by th e port designation. for example, serdes interface signals for port 0 are i dentified as tx_p_0 and tx_n_0. serial designation. a set of signals that are not tied to any specific port are designated by the signal mnemonic, followed by a brackete d serial designation. for example, the set of 11 cpu address bus signals is identified as upx_add[10:0]. port designation . individual signals that apply to a particular port are designated by the signal mnemonic, immediately followed by an underscore and the port designation. for example, rgmii transmit control signals are identified as tx_ctl_0, tx_ctl_1, tx_ctl_2, and so on. port bus designation. a set of bus signals that apply to a particular port are designated by the signal mnemonic, immediately follow ed by a bracketed bus designation, followed by an underscore and the port designation. fo r example, rgmii transmit data bus signals are identified as td[3:0]_0, td [3:0]_1, td[3:0]_2, and so on. active low designation. a control input or indicator ou tput that is active low is designated by a final suffix consisting of an underscore followed by an upper case ?l?. for example, the cpu cycle complete identifier is shown as upx_rdy_l. 4.1.2 register address conventions registers located in on-chip memory are accessed using a register address, which is provided in hex notation. a register address is indicated by the dollar sign ($), followed by the memory location in hex. 4.2 interface signal groups this section describes the ixf1104 mac sign als in groups according to the associated interface or function. figure 4 shows the various interfaces available on the ixf1104 mac. page 39 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 4.3 signal description tables the i/o signals, power supplies, or ground returns associated with each ixf1104 mac connection ball are described in ta b l e 3 through table 14 . figure 4 interface signals tdat[31:0] tfclk tenb_0 terr_0 tprty_0 tmod[1:0] tsx tsop_0 teop_0 tadr[1:0] dtpa_0:3 stpa ptpa rdat[31:0] rfclk renb_0 rval_0 rerr_0 rprty_0 rmod[1:0] rsx rsop_0 reop_0 tms tdi tdo tclk mdio mdc txpauseadd[2:0] txpausefr upx_width[1:0] upx_data[31:0] upx_add[10:0] upx_badd[1:0] upx_wr_l upx_rd_l upx_cs_l upx_rdy_l led_clk led_data led_latch sys_res_l clk125 mod_def_0:3 tx_disable_0:3 tx_fault_0:3 rx_los_0:3 tx_fault_int rx_los_int mod_def_int i 2 c_clk i 2 c_data_0:3 spi3 interface jtag interface mdio interface pause control interface cpu interface led interface system interface gmii rgmii gmii and rgmii interfaces* * data and clock balls are shared for gmii and rgmii interfaces serdes interface optical module interface signals** ** these optical module signals are multiplexed on the gmii balls. rx_p/n_0:3 tx_p/n_0:3 trst_l ixf1104 media access controller b3181-02 mphy sphy tfclk tenb_0:3 terr_0:3 tprty_0:3 tsop_0:3 teop_0:3 tdat[7:0]_0:3 tadr[1:0] dtpa_0:3 ptpa rdat[7:0]_0:3 rfclk renb_0:3 rval_0:3 rerr_0:3 rprty_0:3 rsop_0:3 reop_0:3 txc_0:3 txd[7:0]_3 txc_0:3 td[3:0]_3 txd[7:0]_2 td[3:0]_2 txd[7:0]_1 td[3:0]_1 txd[7:0]_0 td[3:0]_0 tx_en_0:3 tx_er_0:3 tx_ctl_0:3 rxc_0:3 rxc_0:3 rxd[7:0]_3 rd[3:0]_3 rxd[7:0]_2 rd[3:0]_2 rxd[7:0]_1 rd[3:0]_1 rxd[7:0]_0 rd[3:0]_0 rx_dv_0:3 rx_er_0:3 crs_0:3 col_0:3 rx_ctl_0:3 page 40 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 3 spi3 interface signal descriptions (sheet 1 of 8) signal name ball designator type standard description mphy sphy tdat31 tdat30 tdat29 tdat28 tdat27 tdat26 tdat25 tdat24 tdat7_3 tdat6_3 tdat5_3 tdat4_3 tdat3_3 tdat2_3 tdat1_3 tdat0_3 f7 f5 g9 g8 g7 g6 g5 g4 input 3.3 v lvttl transmit data bus. carries payload data to the ixf1104 mac egress path. mode 32-bit multi-phy 4 x 8 single-phy bits [31:24] [7:0] for port 3 tdat23 tdat22 tdat21 tdat20 tdat19 tdat18 tdat17 tdat16 tdat7_2 tdat6_2 tdat5_2 tdat4_2 tdat3_2 tdat2_2 tdat1_2 tdat0_2 c8 f9 e10 e9 e8 e7 e6 e5 input 3.3 v lvttl transmit data bus. carries payload data to the ixf1104 mac egress path. mode 32-bit multi-phy 4 x 8 single-phy bits [23:16] [7:0] for port 2 tdat15 tdat14 tdat13 tdat12 tdat11 tdat10 tdat9 tdat8 tdat7_1 tdat6_1 tdat5_1 tdat4_1 tdat3_1 tdat2_1 tdat1_1 tdat0_1 h3 j3 j2 j1 h1 g2 g1 f1 input 3.3 v lvttl transmit data bus. carries payload data to the ixf1104 mac egress path. mode 32-bit multi-phy 4 x 8 single-phy bits [15:8] [7:0] for port 1 tdat7 tdat6 tdat5 tdat4 tdat3 tdat2 tdat1 tdat0 tdat7_0 tdat6_0 tdat5_0 tdat4_0 tdat3_0 tdat2_0 tdat1_0 tdat0_0 c6 b5 c5 c4 d1 c3 c2 b3 input 3.3 v lvttl transmit data bus. carries payload data to the ixf1104 mac egress path. mode 32-bit multi-phy 4 x 8 single-phy bits 7:0] [7:0] for port 0 tfclk tfclk d7 input 3.3 v lvttl transmit clock. tfclk is the clock associated with all transmit signals. data and control lines are sampled on the rising edge of tfclk (frequency operation range 90 - 133 mhz). tprty_0 tprty_0 tprty_1 tprty_2 tprty_3 d5 g3 b9 j6 input 3.3 v lvttl transmit parity. tprty indicates odd parity for the tdat bus. tprty is valid only when a channel asserts either tenb or tsx. odd parity is the default configuration; however, even parity can be selected (see table 146, spi3 transmit and global configuration ($0x700) , on page 204 ). 32-bit multi-phy mode: tprty_0 is the parity bit covering all 32 bits. 4 x 8 single-phy mode: t prty_0:3 bits correspond to the respective tdat[3:0]_ n channels. page 41 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 tenb_0 tenb_0 tenb_1 tenb_2 tenb_3 b7 e2 c9 j4 input 3.3 v lvttl transmit write enable. tenb_0:3 asserted causes an attached phy to process tdat[ n ], tmod, tsop, teop and terr signals. 32-bit multi-phy mode: tenb_0 is the enable bit for all 32 bits. 4 x 8 single-phy mode: t enb_0:3 bits correspond to the respective tdat[3:0]_ n channels and their associated control and status signals. terr_0 terr_0 terr_1 terr_2 terr_3 a8 k1 e11 j8 input 3.3 v lvttl transmit error. terr indicates that there is an error in the current packet. terr is valid when simultaneously assert ed with teop and tenb. 32-bit multi-phy mode: terr_0 is the bit asserted for all 32 bits. 4 x 8 single-phy mode: each bit of terr_0:3 corresponds to the respective tdat[3:0]_ n channel. tsop_0 tsop_0 tsop_1 tsop_2 tsop_3 c7 e3 c10 j5 input 3.3 v lvttl transmit start-of-packet. tsop indicates the start of a packet and is valid when asserted simultaneously with tenb. 32-bit multi-phy mode: tsop_0 is the bit asserted for all 32 bits. 4 x 8 single-phy mode: each bit of tsop_0:3 corresponds to the respective tdat[3:0]_ n channel. teop_0 teop_0 teop_1 teop_2 teop_3 a7 f3 e4 h5 input 3.3 v lvttl transmit end-of-packet. teop indicates the end of a packet and is valid when asserted simultaneously with tenb. 32-bit multi-phy mode: teop_0 is the bit asserted for all 32 bits. 4 x 8 single-phy mode: each bit of teop_0:3 corresponds to the respective tdat[3:0]_ n channel. table 3 spi3 interface signal descriptions (sheet 2 of 8) signal name ball designator type standard description mphy sphy page 42 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 tmod1 tmod0 na d9 a6 input 3.3 v lvttl tmod[1:0] transmit word modulo. 32-bit multi-phy mode: t mod[1:0] indicates the valid data bytes of tdat[31:0]. during transmission, tmod[1:0] should always be ?00? until the last double word is transferred on tdat[31:0]. tmod[1:0] specifies the valid bytes of tdat when teop is asserted: tmod[1:0] ? valid bytes of tdat 00 = 4 bytes [31:0] 01 = 3 bytes [31:8] 10 = 2 bytes [31:16] 11 = 1 byte [31:24] tenb must be asserted simultaneously for tmod[1:0] to be valid. 4 x 8 single-phy mode: mod[1:0] is not required. tsx na e1 input 3.3 v lvttl transmit start of transfer. 32-bit multi-phy mode: tsx asserted with tenb = 1 indicates that the phy address is present on tdat[7:0]. the valid values on tdat[7:0] are 3, 2, 1, and 0. when tenb = 0, tsx is not used by the phy device. note: only tdat[1:0] are relevant; all other bits are ?don?t care?. 4 x 8 single-phy mode: tsx is not used. tadr1 tadr0 tadr1 tadr0 a12 a11 input 3.3 v lvttl tadr[1:0] transmit phy address. the value on tadr[1:0] selects one of the phy ports that drives the ptpa signal after the rising edge of tfclk. dtpa_0 dtpa_1 dtpa_2 dtpa_3 dtpa_0 dtpa_1 dtpa_2 dtpa_3 d3 l1 a9 j7 output 3.3 v lvttl dtpa_0:3 direct transmit packet available. a direct status indication for transmit fifos of ports 0:3. when high, dtpa indicates that the amount of data in the tx fifo is below the tx fifo high watermark. when the high watermark is crossed, dtpa transitions low to indicate that the tx fifo is almost full. it stays low until the amount of data in the tx fifo goes back below the tx fifo low watermark. at this point, dtpa transitions high to indicate that the programmed number of bytes are now available for data transfers. note: for more information, see ta b l e 132, tx fifo high watermark ports 0 - 3 ($0x600 ? 0x603) , on page 195 and table 133, tx fifo low watermark register ports 0 - 3 ($0x60a ? 0x60d) , on page 196 . dtpa is updated on the rising edge of tfclk. table 3 spi3 interface signal descriptions (sheet 3 of 8) signal name ball designator type standard description mphy sphy page 43 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 stpa na c11 output 3.3 v lvttl selected-phy transmit packet available. stpa is only meaningful in a 32-bit multi- phy mode. stpa is a direct status indication for transmit fifos of ports 0:3. when high, stpa indicates that the amount of data in the tx fifo, specified by the latest in-band address, is below the tx fifo high watermark. when the high watermark is crossed, stpa transitions low to indicate the tx fi fo is almost full. it stays low until the amount of data in the tx fifo goes back below the tx fifo low watermark. at this point, stpa transitions high to indicate that the programmed number of bytes are now available for data transfers. note: for more information, see ta b l e 132, tx fifo high watermark ports 0 - 3 ($0x600 ? 0x603) , on page 195 and table 133, tx fifo low watermark register ports 0 - 3 ($0x60a ? 0x60d) , on page 196 . stpa provides the status indication for the selected port to avoid fifo overflows while polling is performed. the port reported by stpa is updated on the following rising edge of tfclk after tsx is sampled as asserted. stpa is updated on the rising edge of tfclk. ptpa ptpa b11 output 3.3 v lvttl polled-phy transmit packet available. ptpa allows the polling of the port selected by the tadr address bus. when high, ptpa indicates that the amount of data in the tx fifo is below the tx fifo high watermark. when the high watermark is crossed, ptpa transitions low to indicate that the tx fifo is almost full. it stays low until the amount data in the tx fifo goes back below the tx fifo low watermark. at this point, ptpa transitions high to indicate that the programmed number of bytes are now available for data transfers. note: for more information, see ta b l e 132, tx fifo high watermark ports 0 - 3 ($0x600 ? 0x603) , on page 195 and table 133, tx fifo low watermark register ports 0 - 3 ($0x60a ? 0x60d) , on page 196 . the port reported by ptpa is updated on the following rising edge of tfclk after the port address on tadr is sampled by the phy device. ptpa is updated on the rising edge of tfclk. table 3 spi3 interface signal descriptions (sheet 4 of 8) signal name ball designator type standard description mphy sphy page 44 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 rdat31 rdat30 rdat29 rdat28 rdat27 rdat26 rdat25 rdat24 rdat7_3 rdat6_3 rdat5_3 rdat4_3 rdat3_3 rdat2_3 rdat1_3 rdat0_3 f24 g24 g23 g22 g21 g20 g19 g18 output 3.3 v lvttl receive data bus. rdat carries payload data and in-band addresses from the ixf1104 mac. mode 32-bit multi-phy 4 x 8 single-phy bits [31:24] [7:0] for port 3 rdat23 rdat22 rdat21 rdat20 rdat19 rdat18 rdat17 rdat16 rdat7_2 rdat6_2 rdat5_2 rdat4_2 rdat3_2 rdat2_2 rdat1_2 rdat0_2 e21 e22 d22 c22 c21 c20 b22 b20 output 3.3 v lvttl receive data bus. rdat carries payload data and in-band addresses from the ixf1104 mac. mode 32-bit multi-phy 4 x 8 single-phy bits [23:16] [7:0] for port 2 rdat15 rdat14 rdat13 rdat12 rdat11 rdat10 rdat9 rdat8 rdat7_1 rdat6_1 rdat5_1 rdat4_1 rdat3_1 rdat2_1 rdat1_1 rdat0_1 f18 e18 e17 f16 e16 d16 c17 a17 output 3.3 v lvttl receive data bus. rdat carries payload data and in-band addresses from the ixf1104 mac. mode 32-bit multi-phy 4 x 8 single-phy bits [15:8] [7:0] for port 1 rdat7 rdat6 rdat5 rdat4 rdat3 rdat2 rdat1 rdat0 rdat7_0 rdat6_0 rdat5_0 rdat4_0 rdat3_0 rdat2_0 rdat1_0 rdat0_0 f14 e14 d14 c13 c14 b14 a14 a15 output 3.3 v lvttl receive data bus. rdat carries payload data and in-band addresses from the ixf1104 mac. mode 32-bit multi-phy 4 x 8 single-phy bits [7:0] [7:0] for port 0 rfclk rfclk a19 input 3.3 v lvttl receive clock. rfclk is the clock associated with all receive signals. data and controls are driven on the rising edge of rfclk (frequency operation range 90 - 133 mhz). rprty_0 rprty_0 rprty_1 rprty_2 rprty_3 e15 g16 e20 f20 output 3.3 v lvttl receive parity. rprty indicates odd parity for the rdat bus. rprty is valid only when a channel asserts renb or rsx. odd parity is the default configuration; however, even parity can be selected (see table 147 on page 207 ). 32-bit multi-phy mode: rprty_0 is the parity bit for all 32 bits. 4 x 8 single-phy mode: each bit of rprty_0:3 corresponds to the respective rdat[3:0]_ n channel. table 3 spi3 interface signal descriptions (sheet 5 of 8) signal name ball designator type standard description mphy sphy page 45 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 renb_0 renb_0 renb_1 renb_2 renb_3 a13 a18 c19 e24 input 3.3 v lvttl receive read enable. the renb signal controls the flow of data from the receive fifos. during data transfer, rval must be monitored as it indicates if the rdat[31:0], rprty, rmod[1:0], rsop, reop, rerr, and rsx are valid. the system may de-assert renb at any time if it is unable to accept data from the ixf1104 mac. when renb is sampled low, a read is performed from the receive fifo and the rdat[31:0], rprty, rmod[1:0], rsop, reop, rerr, rsx and rval signals are updated on the following rising edge of rfclk. when renb is sampled high by the phy device, a read is not performed, and the rdat[31:0], rprty, rmod[1:0], rsop, reop, rerr, rsx, and rval signals remain unchanged on the following rising edge of rfclk. 32-bit multi-phy mode: renb_0 covers all receive bits. 4 x 8 single-phy mode: the renb_0:3 bits correspond to the per-port data and control signals. rerr_0 rerr_0 rerr_1 rerr_2 rerr_3 a16 g17 d20 h20 output 3.3 v lvttl receive error. rerr indicates that the current packet is in error. rerr is only asserted when reop is asserted. conditions that can cause rerr to be set include fifo overflow, crc error, code error, and runt or giant packets. note: rerr can only be set for these conditions if bit 0 in the section 147, spi3 receive configuration ($0x701) is set to 1. rerr is considered valid only when rval is asserted. 32-bit multi-phy mode: rerr_0 covers all 32 bits. 4 x 8 single-phy mode: the rerr_0:3 bits correspond to the rdat[7:0]_n channels. ( n = 0, 1, 2, or 3) table 3 spi3 interface signal descriptions (sheet 6 of 8) signal name ball designator type standard description mphy sphy page 46 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 rval_0 rval_0 rval_1 rval_2 rval_3 c15 b18 e19 f22 output 3.3 v lvttl receive data valid. rval indicates the validity of the receive data signals. rval is low between transfers and assertion of rsx. it is also low when the ixf1104 mac pauses a transfer due to an empty receive fifo. when a transfer is paused by holding renb high, rval holds its value unchanged, although no new data is present on rdat[31:0] until the transfer resumes. when rval is high, the rdat[31:0], rmod[1:0], rsop, reop, and rerr signals are valid. when rval is low, the rdat[31:0], rmod[1:0], rsop, reop, and rerr signals are invalid and must be disregarded. the rsx signal is valid only when rval is low. 32-bit multi-phy mode: rval_0 covers all receive bits. 4 x 8 single-phy mode: the rval_0:3 bits correspond to the per-port data and control signals. rsop_0 rsop_0 rsop_1 rsop_2 rsop_3 b16 c18 e23 j18 output 3.3 v lvttl receive start of packet. rsop indicates the start of a packet when asserted with rval. 32-bit multi-phy mode: rsop_0 covers all 32 bits. 4 x 8 single-phy mode: the rsop_0:3 bits correspond to the rdat[7:0]_ n channels. table 3 spi3 interface signal descriptions (sheet 7 of 8) signal name ball designator type standard description mphy sphy page 47 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 reop_0 reop_0 reop_1 reop_2 reop_3 c16 d18 c23 j19 output 3.3 v lvttl receive end of packet. reop indicates the end of a packet when asserted with rval. 32-bit multi-phy mode: reop_0 covers all 32 bits. 4 x 8 single-phy mode: the reop_0:3 bits correspond to the rdat[7:0]_ n channels. rmod1 rmod0 na g13 g14 output 3.3 v lvttl receive word modulo: 32-bit multi-phy mode: rmod[1:0] indicates the valid bytes of data in rdat[31:0]. during transmission, rmod is always ?00?, except when the last double- word is transferred on rdat[31:0]. rmod[1:0] specifies the valid packet data bytes on rdat[31:0] when reop is asserted. rmod[1:0] valid bytes of rdat 00 = 4 bytes [31:0] 01 = 3 bytes [31:8] 10 = 2 bytes [31:16] 11 = 1 byte [31:24] 4 x 8 single-phy mode: rmod[1:0] is not required. rmod is considered valid only when rval is simultaneously asserted. renb must be asserted for rmod[1:0] to be valid. rsx na e13 output 3.3 v lvttl receive start of transfer. 32-bit multi-phy mode: rsx indicates when the in-band port address is present on the rdat bus. when rsx is high and rval = 0, the value of rdat[7:0] is the address of the receive fifo to be selected. subsequent data transfers on rdat are from the fifo specified by this in-band address. values of 0, 1, 2, and 3 select the corresponding port. rsx is ignored when rval is de-asserted. 4 x 8 single-phy mode: rsx is ignored. table 3 spi3 interface signal descriptions (sheet 8 of 8) signal name ball designator type standard description mphy sphy page 48 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 4 serdes interface signal descriptions signal name ball designator type standard description tx_p_0 tx_p_1 tx_p_2 tx_p_3 y13 ad13 w16 ac18 output serdes transmit differential output, positive. tx_n_0 tx_n_1 tx_n_2 tx_n_3 y14 ad14 y16 ad18 output serdes transmit differential output, negative. rx_p_0 rx_p_1 rx_p_2 rx_p_3 p22 v22 t24 u24 input serdes receive differential input, positive. 1 rx_n_0 rx_n_1 rx_n_2 rx_n_3 r22 u22 r24 v24 input serdes receive differential input, negative. 1 1. internally terminated differentially with 100 . page 49 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 5 gmii interface signal descriptions (sheet 1 of 2) signal name ball designator type standard description txd7_0 txd6_0 txd5_0 txd4_0 txd3_0 txd2_0 txd1_0 txd0_0 txd7_1 txd6_1 txd5_1 txd4_1 txd3_1 txd2_1 txd1_1 txd0_1 txd7_2 txd6_2 txd5_2 txd4_2 txd3_2 txd2_2 txd1_2 txd0_2 txd7_3 txd6_3 txd5_3 txd4_3 txd3_3 txd2_3 txd1_3 txd0_3 y4 ab4 ac3 ab3 aa3 y3 y2 y1 ac9 ad8 ab8 aa7 ad9 ab9 ab7 ac7 aa18 aa20 ab19 ad16 ab23 ab22 ab21 ab20 w14 aa16 y15 aa14 v17 v16 v15 v14 output 2.5 v cmos transmit data. each bus carries eight data bits [7:0] of the transmitted data stream to the phy device. rgmii mode: when a port is configured in copper mode and the rgmii interface is selected, only bits txd[3:0]_ n are used. the data is transmitted on both edges of txc_0:3. fiber mode: the following signals have multiplexed functions when a port is configured in fiber mode: txd4_ n : tx_disable_0:3 tx_en_0 tx_en_1 tx_en_2 tx_en_3 ab2 y8 ac22 v12 output 2.5 v cmos transmit enable. tx_en indicates that valid data is being driven on the corresponding transmit data: txd_0, txd_1, txd_2, and txd_3. tx_er_0 tx_er_1 tx_er_2 tx_er_3 w1 ad6 ad17 ab13 output 2.5 v cmos transmit error: tx_er indicates a transmit error in the corresponding transmit data: txd_0, txd_1, txd_2, and txd_3. txc_0 txc_1 txc_2 txc_3 aa1 ad7 ac20 ab14 output 2.5 v cmos source synchronous transmit clock. this clock is supplied synchronous to the transmit data bus in either rgmii or gmii mode. note: shares the same balls as rxc on the rgmii interface. note: refer to the rgmii interface for shared data and clock signals. page 50 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 rxd7_0 rxd6_0 rxd5_0 rxd4_0 rxd3_0 rxd2_0 rxd1_0 rxd0_0 rxd7_1 rxd6_1 rxd5_1 rxd4_1 rxd3_1 rxd2_1 rxd1_1 rxd0_1 rxd7_2 rxd6_2 rxd5_2 rxd4_2 rxd3_2 rxd2_2 rxd1_2 rxd0_2 rxd7_3 rxd6_3 rxd5_3 rxd4_3 rxd3_3 rxd2_3 rxd1_3 rxd0_3 ac5 ab5 y5 y6 y7 w7 v7 v8 y10 aa11 ac11 ad10 w9 w11 y11 y9 w20 v19 v20 w22 y23 y22 y21 y20 t19 t18 t17 t16 w18 y19 y18 y17 input 2.5 v cmos receive data: each bus carries eight data bits [7:0] of the received data stream. rgmii mode: when a port id is configured in copper mode and the rgmii interface is selected, only bits rxd[3:0]_ n are used to receive data. fiber mode : the following signals have multiplexed functions when a port is configured in fiber mode: rxd4_ n : mod_def_0:3 rxd5_ n : tx_fault_0:3 rxd6_ n : rx_los_0:3 rx_dv_0 rx_dv_1 rx_dv_2 rx_dv_3 v5 ab11 y24 v18 input 2.5 v cmos receive data valid. rx_dv indicates that valid data is being driven on receive data: rxd[7:0]_ n . rx_er_0 rx_er_1 rx_er_2 rx_er_3 w5 y12 aa22 u20 input 2.5 v cmos receive error. rx_er indicates an error in receive data: rxd[7:0]_ n . crs_0 crs_1 crs_2 crs_3 aa5 aa9 ab15 ac16 input 2.5 v cmos carrier sense. crs indicates the phy device has detected a carrier. rxc_0 rxc_1 rxc_2 rxc_3 v4 ad11 aa24 v23 input 2.5 v cmos receiver reference clock. rxc operates at: 125 mhz for 1 gigabit note: shares the same balls as rxc on the rgmii interface. table 5 gmii interface signal descriptions (sheet 2 of 2) signal name ball designator type standard description note: refer to the rgmii interface for shared data and clock signals. page 51 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 6 rgmii interface signal descriptions (sheet 1 of 2) signal name ball designator type standard description txc_0 txc_1 txc_2 txc_3 aa1 ad7 ac20 ab14 output 2.5 v cmos source synchronous transmit clock. this clock is supplied sync hronous to the transmit data bus in either rgmii or gmii mode. td3_0 td2_0 td1_0 td0_0 td3_1 td2_1 td1_1 td0_1 td3_2 td2_2 td1_2 td0_2 td3_3 td2_3 td1_3 td0_3 aa3 y3 y2 y1 ad9 ab9 ab7 ac7 ab23 ab22 ab21 ab20 v17 v16 v15 v14 output 2.5 v cmos transmit data. bits [3:0] are clocked on the rising edge of txc. bits [7:4] are clocked on the falling edge of txc. note: shares data signals txd[3:0]_ n with the gmii interface. tx_ctl_0 tx_ctl_1 tx_ctl_2 tx_ctl_3 ab2 y8 ac22 v12 output 2.5 v cmos transmit control. tx_ctl is tx_en on the rising edge of txc and a logical derivative of tx_en and tx_er on the falling edge of txc. note: tx_ctl multiplexes with tx_en_ n on the gmii interface. page 52 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 rxc_0 rxc_1 rxc_2 rxc_3 v4 ad11 aa24 v23 input 2.5 v cmos receiver reference clock. operates at: 125 mhz for 1 gigabit 25 mhz for 100 mbps 2.5 mhz for 10 mbps note: shares the same balls as rxc on the gmii interface. rd3_0 rd2_0 rd1_0 rd0_0 rd3_1 rd2_1 rd1_1 rd0_1 rd3_2 rd2_2 rd1_2 rd0_2 rd3_3 rd2_3 rd1_3 rd0_3 y7 w7 v7 v8 w9 w11 y11 y9 y23 y22 y21 y20 w18 y19 y18 y17 input 2.5 v cmos receive data. bits [3:0] are clocked on the rising edge of rxc. bits [7:4] are clocked on the falling edge of rxc. note: shares balls with rxd[3:0]_0 on the gmii interface. rx_ctl_0 rx_ctl_1 rx_ctl_2 rx_ctl_3 v5 ab11 y24 v18 input 2.5 v cmos receive control. rx_ctl is rx_dv on the rising edge of rxc and a logical derivative of rx_dv and rerr on the falling edge of rxc. note: rx_ctl shares the same balls as rx_dv on the gmii interface. table 6 rgmii interface signal descriptions (sheet 2 of 2) signal name ball designator type standard description page 53 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 7 cpu interface signal descriptions (sheet 1 of 2) signal name ball designator type standard description upx_add10 upx_add9 upx_add8 upx_add7 upx_add6 upx_add5 upx_add4 upx_add3 upx_add2 upx_add1 upx_add0 t3 u3 v3 v2 v1 u1 t1 r1 p1 n1 p3 input 3.3 v lvttl upx_add is the address bus from the microprocessor. upx_badd1 upx_badd0 w3 t2 input 3.3 v lvttl 16-bit mode: the data word select uses upx_badd1. 8-bit mode: upx_badd[1:0] selects the individual bytes. upx_data31 upx_data30 upx_data29 upx_data28 upx_data27 upx_data26 upx_data25 upx_data24 upx_data23 upx_data22 upx_data21 upx_data20 upx_data19 upx_data18 upx_data17 upx_data16 upx_data15 upx_data14 upx_data13 upx_data12 upx_data11 upx_data10 upx_data9 upx_data8 upx_data7 upx_data6 upx_data5 upx_data4 upx_data3 upx_data2 upx_data1 upx_data0 l17 j17 h16 j16 m15 n15 k15 h14 k13 g12 k12 g11 h11 g10 k10 m10 n10 j9 h9 l8 n7 l7 l6 p5 k5 m5 n5 l4 m3 l3 k3 l2 input/ output 3.3 v lvttl data bus. 32-bit mode: uses [31:0] 16-bit mode: uses [15:0] 8-bit mode: uses [7:0] upx_cs_l r3 input 3.3 v lvttl chip select. active low. upx_wr_l t4 input 3.3 v lvttl write strobe. active low. upx_rd_l v6 input 3.3 v lvttl read strobe. active low. page 54 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 upx_rdy_l m1 open drain output* 3.3 v lvttl cycle complete indicator. active low. note: an external pull-up resistor is required for proper operation. note: *dual-mode i/o normal operation: open drain output boundary scan mode: standard cmos output upx_width1 upx_width0 t5 u16 input 3.3 v lvttl data bus width select. upx_width[1:0] specifies the cpu bus width. upx_width[1:0] 00 01 1x mode 8-bit 16-bit 32-bit table 7 cpu interface signal descriptions (sheet 2 of 2) signal name ball designator type standard description table 8 transmit pause control interface signal descriptions signal name ball designator type standard description txpauseadd2 txpauseadd1 txpauseadd0 p21 p20 n20 input 2.5 v cmos txpauseadd[2:0] is the port selection address for pause frame insertion. txpausefr t20 input 2.5 v cmos tx pause interface strobe. page 55 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 9 optical module interface signal descriptions (sheet 1 of 2) signal name ball designator type standard description tx_disable_0 tx_disable_1 tx_disable_2 tx_disable_3 ab3 aa7 ad16 aa14 open drain output* 2.5 v cmos transmit disable: tx_disable_0:3 outputs disable the optical module interface transmitter. an external pull-up resistor usually resident in an optical module is required for proper operation. note: these signals are multiplexed with the txd[4]_ n bits of the gmii interface note: *dual-mode i/o normal operation: open drain output boundary scan mode: standard cmos output mod_def_0 mod_def_1 mod_def_2 mod_def_3 y6 ad10 w22 t16 input 2.5 v cmos mod_def_0:3 inputs determine when an optical module interface is present. note: these signals are multiplexed with the rxd[4]_ n bits of the gmii interface. rx_los_0 rx_los_1 rx_los_2 rx_los_3 ab5 aa11 v19 t18 input 2.5 v cmos rx_los_0:3 inputs determine when the optical module interface receiver loses synchronization. note: these signals are multiplexed with the rxd[6]_ n bits of the gmii interface. tx_fault_0 tx_fault_1 tx_fault_2 tx_fault_3 y5 ac11 v20 t17 input 2.5 v cmos tx_fault_0:3 inputs determine an optical module interface transmitter fault. note: these signals are multiplexed with the rxd[5]_ n bits of the gmii interface. rx_los_int p19 open drain output* 2.5 v cmos receiver loss of signal interrupt. rx_los_int is an open drain interrupt output to signal an rx_los condition. note: an external pull-up resistor is required for proper operation. note: *dual-mode i/o normal operation: open drain output boundary scan mode: standard cmos output tx_fault_int p23 open drain output* 2.5 v cmos transmitter fault interrupt. tx_fault_int is an open drain interrupt output that signals a tx_fault condition. note: an external pull-up resistor is required for proper operation. note: *dual-mode i/o normal operation: open drain output boundary scan mode: standard cmos output page 56 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 mod_def_int n22 open drain output* 2.5 v cmos module definition interrupt . mod_def_int is an open drain interrupt output that signals a mod_def condition. note: an external pull-up resistor is required for proper operation. note: *dual-mode i/o normal operation: open drain output boundary scan mode: standard cmos output i 2 c_clk l23 output 2.5 v cmos i 2 c_clk is the clock used for the i 2 c bus interface. i 2 c data_0 i 2 c data_1 i 2 c data_2 i 2 c data_3 l24 m24 n24 p24 input/ open drain output* 2.5 v cmos i 2 c data bus. i 2 c data_0:3 are the data i/os for the i 2 c bus interface. note: an external pull-up resistor is required for proper operation. note: *dual-mode i/o normal operation: input/ open drain output boundary scan mode: standard cmos output table 9 optical module interface signal descriptions (sheet 2 of 2) signal name ball designator type standard description table 10 mdio interfac e signal descriptions signal name ball designator type standard description mdio v21 input/ output 2.5 v cmos mdio is the management data input and output. note: an external pull-up resi stor is required for proper operation. mdc w24 output 2.5 v cmos mdc is the management clock to external devices. table 11 led interface signal descriptions signal name ball designator type standard description led_clk k24 output 2.5 v cmos led_clk is the clock output for the led block. led_data m22 output 2.5 v cmos led_data is the data output for the led block. led_latch l22 output 2.5 v cmos led_latch is the latch enable for the led block. page 57 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 12 jtag interface signal descriptions signal name ball designator type standard description tclk j22 input 3.3 v lvttl jtag test clock tms h22 input 3.3 v lvttl test mode select tdi j24 input 3.3 v lvttl test data input tdo h24 output 3.3 v lvttl test data output trst_l j23 input 3.3 v lvttl test reset; reset input for jtag test table 13 system interface signal descriptions signal name ball designator type standard description clk125 ad19 input 2.5 v cmos clk125 is the input clock to pll; 125 mhz +/- 50 ppm sys_res_l ad12 input 2.5 v cmos sys_res_l is the system hard reset (active low). table 14 power supply signal descriptions (sheet 1 of 2) signal name ball designator type standard description gnd a4 b15 d12 f2 f19 h12 j10 k9 k19 l12 m4 m17 n11 p10 r2 r11 r23 u8 u21 w15 aa8 aa21 ac14 a21 b19 d13 f6 f23 h13 j15 k11 k23 l13 m8 m21 n14 p12 r6 r14 t10 u12 w2 w19 aa12 ab12 ac15 b6 d4 d17 f10 h4 h17 k2 k14 l5 l15 m11 n4 n17 p13 r7 r16 t15 u13 w6 w23 aa13 ac6 ac19 b10 d8 d21 f15 h8 h21 k6 k16 l10 l20 m14 n8 n21 p15 r9 r19 u4 u17 w10 aa4 aa17 ac10 ad21 input ? digital ground avdd1p8_1 a5 a20 input 1.8 v analog 1.8 v supply avdd1p8_2 ab16 t23 input 1.8 v analog 1.8 v supply avdd2p5_1 ad20 input 2.5 v analog 2.5 v supply page 58 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 4.4 ball usage summary avdd2p5_2 u14 r18 input 2.5 v analog 2.5 v supply vdd a10 d11 f21 j14 k17 l14 p14 r17 u10 aa6 c12 d15 h10 j20 k21 l16 p16 r21 u15 aa10 d6 d19 h15 k4 l9 p9 r4 t11 w4 aa15 d10 f4 j11 k8 l11 p11 r8 t14 w21 aa19 input 1.8 v digital 1.8 v supply vdd2 b4 f8 j12 m12 b8 f12 m2 b12 h2 m6 d2 h6 m9 input 3.3 v digital 3.3 v supply vdd3 b13 f13 j13 m23 b17 f17 m13 b21 h19 m16 d23 h23 m19 input 3.3 v digital 3.3 v supply vdd4 n13 t13 w17 ac21 n16 u19 aa23 n19 u23 ac13 n23 w13 ac17 input 2.5 v digital 2.5 v supply vdd5 n2 t12 w12 ac12 n6 u2 aa2 n9 u6 ac4 n12 w8 ac8 input 2.5 v digital 2.5 v supply table 14 power supply signal descriptions (sheet 2 of 2) signal name ball designator type standard description table 15 ball usage summary type quantity inputs 158 outputs 126 bi-directional 37 total signals 321 power 75 ground 82 no connects 74 total 552 page 59 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 4.5 multiplexed ball connections 4.5.1 gmii/rgmii/serdes/omi multiplexed ball connections table 16 lists the balls used for the line-side in terfaces (gmii, rgmii, serdes/omi) and provides a guide to connect these balls. some of these balls are multiplexed depending on the mode of operation selected for that port. note: do not connect any balls marked as unused (nc). table 16 line side interface multiplexed balls (sheet 1 of 2) copper mode fiber mode unused port ball designator gmii signal rgmii signal optical module/ serdes signal txc_0:3 txc_0:3 nc nc aa1 ad7 ac20 ab14 txd[3:0]_0 txd[3:0]_1 txd[3:0]_2 txd[3:0]_3 td[3:0]_0 td[3:0]_1 td[3:0]_2 td[3:0]_3 nc nc aa3 ad9 ab23 v17 y3 ab9 ab22 v16 y2 ab7 ab21 v15 y1 ac7 ab20 v14 txd4_0:3 nc tx_disable_0:3 2 nc ab3 aa7 ad16 aa14 txd[7:5]_0 txd[7:5]_1 txd[7:5]_2 txd[7:5]_3 nc nc nc y4 ac9 aa18 w14 ab4 ad8 aa20 aa16 ac3 ab8 ab19 y15 tx_en_0:3 tx_ctl_0:3 nc nc ab2 y8 ac22 v12 tx_er_0:3 nc nc nc w1 ad6 ad17 ab13 rxc_0:3 rxc_0:3 gnd gnd v4 ad11 aa24 v23 rxd[3:0]_0 rxd[3:0]_1 rxd[3:0]_2 rxd[3:0]_3 rd[3:0]_0 rd[3:0]_1 rd[3:0]_2 rd[3:0]_3 gnd gnd y7 w9 y23 w18 w7 w11 y22 y19 v7 y11 y21 y18 v8 y9 y20 y17 rxd4_0:3 gnd mod_def_0:3 1 gnd y6 ad10 w22 t16 rxd5_0:3 gnd tx_fault_0:3 1 gnd y5 ac11 v20 t17 rxd6_0:3 gnd rx_los_0:3 1 gnd ab5 aa11 v19 t18 rxd7_0:3 gnd gnd gnd ac5 y10 w20 t19 rx_dv_0:3 rx_ctl_0:3 gnd gnd v5 ab11 y24 v18 rx_er_0:3 gnd gnd gnd w5 y12 aa22 u20 crs_0:3 gnd gnd gnd aa5 aa9 ab15 ac16 col_0:3 gnd gnd gnd ab6 ab10 ad15 ab17 gnd gnd rx_p_0:3 gnd p22 v22 t24 u24 gnd gnd rx_n_0:3 gnd r22 u22 r24 v24 nc nc tx_p_0:3 nc y13 ad13 w16 ac18 nc nc tx_n_0:3 nc y14 ad14 y16 ad18 nc nc tx_fault_int 2 nc p23 1. an external pull-up resistor is required with most optical modules. 2. an open drain i/o, external 4.7 k pull-up resistor is required. page 60 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 4.5.2 spi3 mphy/sphy ball connections table 17 lists the balls used for the spi3 interface and provides a guide to connect these balls in mphy and sphy mode. nc nc rx_los_int 2 nc p19 nc nc mod_def_int 2 nc n22 mdc mdc nc nc w24 mdio 2 mdio 2 nc nc v21 nc nc i 2 c_clk nc l23 nc nc i 2 c_data_0:3 2 nc l24 m24 n24 p24 table 16 line side interface multiplexed balls (sheet 2 of 2) copper mode fiber mode unused port ball designator gmii signal rgmii signal optical module/ serdes signal 1. an external pull-up resistor is required with most optical modules. 2. an open drain i/o, external 4.7 k pull-up resistor is required. table 17 spi3 mphy/sphy interface (sheet 1 of 3) spi3 signals ball number comments mphy sphy tdat[31:24] tdat[7:0]_3 f7 g7 f5 g6 g9 g5 g8 g4 mphy: consists of a single 32-bit data bus sphy: separate 8-bit data bus for each ethernet port tdat[23:16] tdat[7:0]_2 c8 e8 f9 e7 e10 e6 e9 e5 tdat[15:8] tdat[7:0]_1 h3 h1 j3 g2 j2 g1 j1 f1 tdat[7:0] tdat[7:0]_0 c6 d1 b5 c3 c5 c2 c4 b3 tfclk tfclk d7 to achieve maximum bandwidth, set tfclk as follows: mphy: 133 mhz sphy: 125 mhz. tprty_0 tprty_0 d5 mphy: use tprty_0 as the tprty signal. sphy: each port has its own dedicated tprty_ n signal. gnd tprty_1 g3 gnd tprty_2 b9 gnd tprty_3 j6 tenb_0 tenb_0 b7 mphy: use tenb_0 as the tenb signal. sphy: each port has its own dedicated tenb_ n signal. vdd2 tenb_1 e2 vdd2 tenb_2 c9 vdd2 tenb_3 j4 page 61 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 terr_0 terr_0 a8 mphy: use terr_0 as the terr signal. sphy: each port has its own dedicated terr_ n signal gnd terr_1 k1 gnd terr_2 e11 gnd terr_3 j8 tsop_0 tsop_0 c7 mphy: use tsop_0 as the tsop signal. sphy: each port has a dedicated tsop_ n signal. gnd tsop_1 e3 gnd tsop_2 c10 gnd tsop_3 j5 teop_0 teop_0 a7 mphy: use teop_0 as the teop signal. sphy: each port has a dedicated teop_ n signal. gnd teop_1 f3 gnd teop_2 e4 gnd teop_3 h5 tmod[1:0] gnd d9 a6 tsx and tmod[1:0] are only applicable in mphy mode. tsx gnd e1 tadr[1:0] tadr[1:0] a12 a11 used to address port for ptpa signal. ptpa ptpa b11 ptpa can be used in mphy and sphy modes. dtpa_0:3 dtpa_0:3 d3 l1 a9 j7 dtpa is available on a per-port basis in both mphy and sphy modes. stpa nc c11 stpa is only applicable in mphy mode. rdat[31:24] rdat[7:0]_3 f24 g21 g24 g20 g23 g19 g22 g18 mphy: consists of a single 32 bit data bus. sphy: separate 8-bit data bus for each ethernet port. rdat[23:16] rdat[7:0]_2 e21 c21 e22 c20 d22 b22 c22 b20 rdat[15:8] rdat[7:0]_1 f18 e16 e18 d16 e17 c17 f16 a17 rdat[7:0] rdat[7:0]_0 f14 c14 e14 b14 d14 a15 c13 a14, rfclk rfclk a19 to achieve maximum bandwidth, set rfclk as follows: mphy: 133 mhz. sphy: 125 mhz. rprty_0 rprty_0 e15 mphy: use rprty_0 as the rprty signal. sphy: each port has a dedicated rprty_ n signal. nc rprty_1 g16 nc rprty_2 e20 nc rprty_3 f20 renb_0 renb_0 a13 mphy: use renb_0 as the renb signal. sphy: each port has a dedicated renb_ n signal vdd2 renb_1 a18 vdd2 renb_2 c19 vdd2 renb_3 e24 table 17 spi3 mphy/sphy interface (sheet 2 of 3) spi3 signals ball number comments mphy sphy page 62 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 4.6 ball state during reset rerr_0 rerr_0 a16 mphy: use rerr_0 as the rerr signal. sphy: each port has a dedicated rerr_ n signal nc rerr_1 g17 nc rerr_2 d20 nc rerr_3 h20 rval_0 rval_0 c15 mphy: use rval_0 as the rval signal. sphy: each port has a dedicated rval_ n signal. nc rval_1 b18 nc rval_2 e19 nc rval_3 f22 rsop_0 rsop_0 b16 mphy: use tsop_0 as the tsop signal. sphy: each port has a dedicated tsop_ n signal. nc rsop_1 c18 nc rsop_2 e23 nc rsop_3 j18 reop_0 reop_0 c16 mphy: use teop_0 as the teop signal. sphy: each port has a dedicated teop_ n signal. nc reop_1 d18 nc reop_2 c23 nc reop_3 j19 rmod[1:0] nc g13 g14 rsx and rmod[1:0] are applicable only in mphy mode. rsx nc e13 table 17 spi3 mphy/sphy interface (sheet 3 of 3) spi3 signals ball number comments mphy sphy table 18 definition of ou tput and bi-directional balls during hardware reset (sheet 1 of 2) interface ball name ball reset state comment spi3 dtpa_0:3 0x0 ? stpa 0x0 ? ptpa 0x0 ? rdat[31:0] 0x00000000 ? rval_0:3 0x0 ? rerr_0:3 0x0 ? rprty_0:3 0x0 ? rmod[1:0] 0x0 ? rsx 0x0 ? rsop_0:3 0x0 ? reop_0:3 0x0 ? note: z = high impedance. page 63 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 4.7 power supply sequencing follow the power-up and power-down sequences described in this section to ensure correct ixf1104 mac operation. the sequence described in section 4.7 covers all ixf1104 mac digital and analog supplies. caution: failure to follow the sequence described in this section might damage the ixf1104 mac. jtag tdo 0x0 ? mdio mdio high z bi-directional mdc 0x0 ? cpu upx_data[31:0] high z bi-directional upx_rdy_l 0x1 open-drain output, requires an external pull-up led led_clk 0x0 ? led_data 0x0 ? led_latch 0x0 ? gmii/rgmii txc_0:3 high z fiber mode is the default. copper interfaces are disabled. txd[7:0]_0 high z fiber mode is the default. bit 4 is driven by the opt ical module as mod_def_0. txd[7:0]_1 high z fiber mode is the default. bit 4 is driven by the opt ical module as mod_def_1. txd[7:0]_2 high z fiber mode is the default. bit 4 is driven by the opt ical module as mod_def_2. txd[7:0]_3 high z fiber mode is the default. bit 4 is driven by the opt ical module as mod_def_3. tx_en_0:3 high z fiber mode is the default. copper interfaces are disabled. tx_er_0:3 high z fiber mode is the default. copper interfaces are disabled. rgmii tx_ctl_0:3 high z fiber mode is the default. copper interfaces are disabled. serdes tx_p_0:3 0x0 ? tx_n_0:3 0x0 ? optical module tx_fault_int high z open-drain output, requires external pull-up. rx_los_int high z open-drain out put, requires external pull-up. mod_def_int high z open-drain out put, requires external pull-up. i 2 c_clk 0x1 ? i 2 c_data_0:3 0xf open-drain output, requires external pull-up. table 18 definition of ou tput and bi-directional balls during hardware reset (sheet 2 of 2) interface ball name ball reset state comment note: z = high impedance. page 64 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 4.7.1 power-up sequence ensure that the 1.8 v analog and digital supplies are applied and stable prior to application of the 2.5 v analog and digital supplies. 4.7.2 power-down sequence remove the 2.5 v supplies prior to removing the 1.8 v power supplies (the reverse of the power-up sequence). caution: damage can occur to the esd structures with in the analog i/os if the 2.5 v digital and analog supplies exceed the 1.8 v digital and analog supplies by more than 2.0 v during power-up or power-down. figure 5 and table 19 provide the ixf1104 mac power supply sequencing. 4.8 pull-up/pull-down ball guidelines the signals shown in table 20 require the addition of a pull-up or pull-down resistor to the board design for normal operation. any balls marked as unused (nc) should be unconnected. figure 5 power supply sequencing time t=0 1.8 v supplies stable 2.5 v supplies stable sys_res apply vdd, avdd1p8_1, and avdd1p8_2 apply vdd4, vdd5, avdd2p5_1 and avdd2p5_2 note: the 3.3 v supply (vdd2 and vdd3) can be appl ied at any point during this sequence. table 19 power supply sequencing power supply power-up order time delta to next supply 1 notes vdd, avdd1p8_1, avdd1p8_2 first 0 1.8 v supplies vdd4, vdd5, avdd2p5_1, avdd2p5_2 second 10 s 2.5 v supplies 1. the value of 10 s given is a nominal value only. the exact time difference between the application of the 2.5 v analog supply is determined by a number of factors, depending on the power management method used. note: to avoid damage to the ixf1104 mac, the txav25 supply must not exceed the vdd supply by more than 2 v at any time during the power-up or power-down sequence. note: the 3.3 v supply (vdd2 and vdd3) can be a pplied at any point during this sequence. page 65 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 4.9 analog power filtering table 21 illustrates an analog power supply filter network and table 21 lists the analog power balls. table 20 pull-up/pull-down and unused ball guidelines pin name pull-up/pull-down comments tx_fault_int pull-up 4.7 k to 2.5 v. optical module signal with open-drain i/o. rx_los_int pull-up 4.7 k to 2.5 v. optical module signal with open-drain i/o. mod_def_int pull-up 4.7 k to 2.5 v. optical module signal with open-drain i/o. tdi pull-up 10 k to 3.3 v. jtag test pin. tdo pull-up 10 k to 3.3 v. jtag test pin. tms pull-up 10 k to 3.3 v. jtag test pin. tclk pull-up 10 k to 3.3 v. jtag test pin. trst_l pull-down 10 k to 3.3 v. jtag test pin. mdio pull-up 4.7 k to 2.5 v upx_rdy_l pull-up 4.7 k to 3.3 v i 2 c_data_0:3 pull-up 4.7 k to 2.5 v tx_disable_0:3 pull-up 4.7 k to 2.5 v figure 6 analog power supply filter network table 21 analog power balls signal name ball designator comments avdd1p8_1 a5 a20 need to provide a filter (see figure 6 ). r: avdd1p8_1 and avdd2p5_1 = 5.6 resistor. avdd2p5_1 ad20 avdd1p8_2 ab16 t23 need to provide a filter (see figure 6 ). r: avdd1p8_2 and avdd2p5_2 = 1.0 resistor. avdd2p5_2 u14 r18 page 66 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.0 functional descriptions 5.1 media access controller (mac) the ixf1104 mac main functional block consists of four independent 10/100/1000 mbps ethernet macs, which support interfaces for fiber and copper connectivity. ? copper mode: ? rgmii for 10/100/1000 mbps full-duplex operation and 10/100 mbps half-duplex operation ? gmii for 1000 mbps full-duplex operation ? fiber mode: ? integrated serdes/omi interface for direct connection to optical modules ? 1000 mbps full-duplex operation in fiber mode the following features support copper and fiber modes: ? programmable options: ? automatic padding of transmitted packets that are less than the minimum frame size ? broadcast, multicast, and unicast address filtering on frames received ? filter and drop packets with errors ? pre-padded rx frames with two bytes (aligns the ethernet payload on spi3 and in network processor memories) ? remove crc from rx frames ? append crc to transmitted frames ? performance monitoring and diagnostics: ? loopback modes ? detection of runt and overly large packets ? cyclic redundancy check (crc) calculation and error detection ? rmon statistics for dropped packets, packets with errors, etc. ? compliant with ieee spec 802.3x standard for flow control ? receive and execute pause command frames ? support for non-standard packet sizes up to 10 kb including loss-less flow control note: the ixf1104 mac does not support 10/100 mbps operation when configured in gmii mode. the ixf1104 mac is fully integrated, designed for use with ethernet 802.3 frame types, and compliant to all of the ieee 802.3 mac requirements. the ixf1104 mac adds preamble and start-of-f rame delimiter (sfd) to all frames sent to it (transmit path) and removes preamble and sfd on all frames rece ived by it (receive path). a crc check is also applied to all tran smit and receive packets. crc is optionally appended to transmit packets. crc is remo ved optionally from receive packets after validation, and is not forwarded to spi3. packets with a bad crc are marked, counted in the statistics block, and may be optionally dropped. a bad packet may be signaled with rerr on the spi3 interface if it is not dropped. page 67 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 the ixf1104 mac operates only in full-duplex mode at 1000 mbps rates on both serdes and gmii interface connection s. the ixf1104 mac is capable of operation at 1000 mbps, full-duplex in rgmii mode, and at full-duplex and half-duplex operation for 10/100 mbps links. 5.1.1 features for fiber and copper mode section 5.1.1.1 through section 5.1.1.4 cover ixf1104 mac functions that are independent of the line-side interface. 5.1.1.1 padding of unders ized frames on transmit the padding feature allows ethernet frames smaller than 64 bytes to be transferred from the spi3 interface to the tx mac and padded up to 64 bytes automatically by the mac. this feature is enabled by setting bit 7 of the diverse config write ($ port_index + 0x18) . note: when the user selects the padding function, the mac core adds an automatically calculated crc to the end of the transmitted packet. 5.1.1.2 automatic crc generation automatic crc generation is used in conjunction with the padding feature to generate and append a correct crc to any transmit fram e. this feature is enabled by setting bit 6 of the diverse config write ($ port_index + 0x18) . 5.1.1.3 filtering of receive packets this feature allows the ixf1104 mac to filt er receive packets under various conditions and drop the packets through an interaction with the receive fifo control. 5.1.1.3.1 filter on unicast packet match this feature is enabled when bit 0 of the rx packet filter control ($ port_index + 0x19) = 1. any frame received in this mode that does not match the station address (mac address) is marked by the ixf1104 mac to be dropped. the frame is dropped if the appropriate bit in the rx fifo errored frame drop enable ($0x59f) = 1. otherwise, the frame is sent out the spi3 interface and may op tionally be signaled with an rerr (see bit 0 in section table 147, spi3 receive configuration ($0x701) , on page 207 ). when bit 0 of the rx packet filter control ($ port_index + 0x19) = 0, all unicast frames are sent out the spi3 interface. note: the vlan filter overrides the unicast filter. therefore, a vlan frame cannot be filtered based on the unicast address. 5.1.1.3.2 filter on multicast packet match this feature is enabled when bit 1 of the rx packet filter control ($ port_index + 0x19) = 1. any frame received in this mode that does not match the port multicast address (reserved multicast address recognized by ixf1104 mac) is marked by the mac to be dropped. the frame is dropped if the appropriate bit in the rx fifo errored frame drop enable ($0x59f) = 1. otherwise, the frame is sent out the spi3 interface and may optionally be signaled with an rerr (see bit 0 in section table 147, spi3 receive configuration ($0x701) , on page 207 ). when bit 1 of the rx packet filter control ($ port_index + 0x19) = 0, all multicast frames are sent out the spi3 interface. page 68 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.1.1.3.3 filter broadcast packets this feature is enabled when bit 2 of the rx packet filter control ($ port_index + 0x19) = 1. any broadcast frame received in this mode is marked by the mac to be dropped. the frame is dropped if the appropriate bit in the rx fifo errored frame drop enable ($0x59f) = 1. otherwise, the frame is sent out the spi3 interface and may optionally be signaled with an rerr (see bit 0 in section table 147, spi3 receive configuration ($0x701) , on page 207 ). when bit 2 of the rx packet filter control ($ port_index + 0x19) = 0, all broadcast frames are sent out the spi3 interface. 5.1.1.3.4 filter vlan packets this feature is enabled when bit 3 of the rx packet filter control ($ port_index + 0x19) = 1. vlan frames received in this mode are marked by the mac to be dropped. the frame is dropped if the appropriate bit in the rx fifo errored frame drop enable ($0x59f) = 1. otherwise, the vlan frame is sent out the spi3 interface and may optionally be signaled with an rerr (see bit 0 in section table 147, spi3 receive configuration ($0x701) , on page 207 ). when bit 3 of the rx packet filter control ($ port_index + 0x19) = 0, all vlan frames are sent out the spi3 interface. 5.1.1.3.5 filter pause packets this feature is enabled when bit 4 of the rx packet filter control ($ port_index + 0x19) = 0. pause frames received in this mode are marked by the mac to be dropped. the frame is dropped if the appropriate bit in the rx fifo errored frame drop enable ($0x59f) = 1. otherwise, the pause frame is sent out the spi3 interface and may optionally be signaled with an rerr (see bit 0 in section table 147, spi3 receive configuration ($0x701) , on page 207 ). when bit 4 of the rx packet filter control ($ port_index + 0x19) = 1, all pause frames are sent out the spi3 interface. note: pause packets are not filtered if flow control is disabled in the section 84, fc enable ($ port_index + 0x12) . 5.1.1.3.6 filter crc error packets this feature is enabled when bit 5 of the section 91, rx packet filter control ($ port_index + 0x19) = 0. frames received with an errored crc are marked as bad frames and may optionally be dropped in the rx fifo. otherwise, the frames are sent to the spi3 interface and may be optiona lly signaled with an rerr (see table 22, crc errored packets drop enable behavior , on page 69 ). when the crc error pass filter bit = 0 ( section 91, rx packet filter control ($ port_index + 0x19) ), it takes precedence over the othe r filter bits. any packet (pause, unicast, multicast or broadcast packet) with a crc error will be marked as a bad frame when the crc error pass filter bit = 0. page 69 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.1.1.4 crc error detection frames received by the mac are checked for a correct crc. when an incorrect crc is detected on a received frame, the rx fcserror rmon statistic counter increments for each crc errored frame. received frames with crc errors may optio nally be dropped in the rx fifo (refer to section 5.1.1.3.6, filter crc error packets , on page 68 ). otherwise, the frames are sent to the spi3 interface and may be dropped by the switch or system controller. frames transmitted by the mac are also checked for correct crc. when an incorrect crc is detected on a transm itted frame, the tx crcerro r rmon statistic counter increments for each incorrect frame. 5.1.2 flow control flow control is an i eee 802.3x-defined mechanism for one networ k node to request that its link partner take a temporary ?pause? in packet transmission. this allows the requesting network node to prevent fifo overruns and dropped packets, by managing incoming traffic to fit its available memory. the temporary pause allows the device to process packets already received or in transi t, thus freeing up the fifo space allocated to those packets. table 22 crc errored pack ets drop enable behavior crc error pass 1 rx fifo erroredframe drop enable 2 rerr enable 3 actions 1xx when crc errored pass = 1, crc errored packets are not filtered and are passed to the spi3 interface. they are not marked as bad, cannot be dropped, and cannot be signaled with rerr. 001 packets are marked as bad but not dropped in the rx fifo. these packets are sent to the spi3 interface, and are signaled with an rerr to the switch or network processor. 000 packets are marked as bad but not dropped in the rx fifo. these packets are sent to the spi3 interface, and are not signaled with an rerr. 01x crc errored packets are marked as bad, dropped in the rx fifo, and never appear at the spi3 interface. note: packet sizes above the rx fifo transfer threshold (see table 128 through table 131 ) cannot be dropped in the rx fifo and are passed to the spi3 interface. these packets can optionally be signaled with rerr on the spi3 interface if the rerr enable bit = 1. 1. see table 91, rx packet filter control ($ port_index + 0x19) , on page 165 . 2. see table 123, rx fifo errored frame drop enable ($0x59f) , on page 189 . 3. see table 147, spi3 receive configuration ($0x701) , on page 207 . note: x = ?don?t care? page 70 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 the ixf1104 mac mac implements the ieee 80 2.3x standard rx fifo threshold-based flow control in copper and fiber modes. when appropriately programmed, the mac can both generate and respond to ieee standard pause frames in full-duplex op eration. the ixf1104 mac also supports externally triggered flow control through the transmit pause control interface. in half-duplex operation, the mac generates collisions instead of sending pause frames to manage the incoming traffic from the link partner 5.1.2.1 802.3x flow contro l (full-duplex operation) the ieee 802.3x standar d identifies four options rela ted to system flow control: ?no pause ? symmetric pause (both directions) ? asymmetric pause (receive direction only) ? asymmetric pause (transmit direction only) the ixf1104 mac supports all four options on a per-port basis. bits 2:0 of the table 84 on page 160 provide programmable control for enabling or disabling flow control in each direction independently. the ieee 802.3x flow contro l mechanism is acco mplished within the mac sublayer, and is based on rx fifo thresholds called waterm arks. the rx fifo level rises and falls as packets are received and processed. when the rx fifo reaches a watermark (either exceeding a high or dropping below a low after exceeding a high), the ixf1104 mac control sublayer signals an internal state ma chine to transmit a pa use frame. the fifos automatically generate pause frames (also calle d control frames) to in itiate the following: ? halt the link partner when the high watermark is reached. ? restart the link partner when the data stored in the fifo falls below the low watermark. figure 7 illustrates the ieee 802.3 fifo flow control functions. page 71 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.1.2.1.1 pause frame format pause frames are mac control frames that are padded to the minimum size (64 bytes). figure 8 and figure 9 illustrate the frame format and contents. figure 7 packet buffering fifo mdi high watermark data flow mac transfer threshold low watermark high watermark data flow low watermark rx fifo high txpausefr (external strobe) 802.3x pause frame generation tx fifo tx side mac rx fifo 802.3 flow control rx side mac spi3 interface b3231-01 figure 8 ethernet frame format number of bytes note: !""# $ % ! &"# page 72 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 an ieee 802.3 mac pause frame is identifi ed by detecting all of the following: ? opcode of 00-01 ? length/type field of 88-08 ? da matching the unique multicast address (01-80-c2-00-00-01) xoff. a pause frame informs the link partner to halt transmission for a specified length of time. the pauselength octets specify the dura tion of the no-transmit period. if this time is greater than zero, the link partner must st op sending any further packets until this time has elapsed. this is referred to as xoff. xon. the mac continues to transmit pause frames with the specified pause length as long as the fifo level exceeds the threshold. if the fifo level falls below the threshold before the pause length time expires, the mac sends another pause frame with the pause length time specified as zero. this is referred to as xo n and informs the link partner to resume normal transmission of packets. 5.1.2.1.2 pause settings the mac must send pause frames repeatedly to maintain the link partner in a pause state. the following two inter-related variables control this process: ? pause length is the amount of time, measured in multiples of 512 bit times, that the mac requests the link partner to halt transmission for. ? pause threshold is the amount of time, measur ed in multiples of 512 bit times, prior to the expiration of the pause length that th e mac transmits another pause frame to maintain the link partner in the pause state. the transmitted pause length in the ixf1104 mac is set by the table 75 on page 157 . the ixf1104 mac pause frame transmission interval is set by the table 80 on page 159 . 5.1.2.1.3 response to received pause command frames when flow control is enabled in th e receive direction (bit 0 in the fc enable ($ port_index + 0x12) ), the ixf1104 mac responds to pause command frames received from the link partner as follows: 1. the ixf1104 mac checks the entire frame to verify that it is a valid pause control frame addressed to the multicast address 01-80-c2 -00-00-01 (as s pecified in ieee figure 9 pause frame format !" #$%&' !()&' " *& +$ &' +, ')& &- &' ., / 0 &' 1 & &') &' &) & 2 .' 3, )$&0 0 &' 1 () &') &' &) & &' 1 2 page 73 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 802.3, annex 31b) or has a destinations address matching the address programmed in the station address ($ port_index +0x00 ? +0x01) . 2. if the pause frame is valid, the transmit side of the ixf1104 mac pauses for the required number of pause quanta, as specified in i eee 802.3, clause 31. 3. pause does not begin until completion of the frame currently being transmitted. the ixf1104 mac response to valid received pause frames is independent of the pause frame filter settings. refer to section 5.1.1.3.5, filter pause packets , on page 68 for additional details. note: pause packets are not filtered if flow control is disabled in bit 0 of the section 84, fc enable ($ port_index + 0x12) . 5.1.2.1.4 half-duplex operation transmit flow control is implemented only in half-duplex operation. upon entering the flow control state, the ma c generates a collision for all subsequent receive packets until exiting the flow control state. any receiv e packet in progress when the mac enters the flow control state will not be collided with but coul d be lost due if there is insufficient fifo depth to complete packet reception. bit 2 of the fc enable ($ port_index + 0x12) enables the transmit flow control function. 5.1.2.1.5 transmit pause control interface the transmit pause control interface allows an external device to trigger the generation of pause frames. the transmit pause control interface is completely asynchronous. it consists of three address signals (t xpauseadd[2:0]) and a strobe signal (txpausefr). the required address for this interface operation is placed on the txpauseadd[2:0] signals and the txpausefr is pulsed high and returned low. refer to figure 10, transmit pause control interface , on page 74 and table 55, transmit pause control interface timing parameters , on page 145 . table 23 shows the valid decodes for the txpauseadd[2:0] signals. figure 10 illustrates the transmit pause control interface. note: flow control must be enabled in the section 84, fc enable ($ port_index + 0x12) for transmit pause control interface operation. note: there are two additional decodes provided that allow the user to generate either an xoff frame or xon frame from all ports simultaneously. the default pause quanta for each port is held by the fc tx timer value ($ port_index + 0x07) ). the default value of this regist er is 0x05e after reset is applied. table 23 valid decodes for txpauseadd[2:0] (sheet 1 of 2) txpauseadd_2:0 operation of tx pause control interface 0x0 transmits a pause frame on every port with a pause_time = zero (xon) (cancels all previous pause commands). 0x1 transmits a pause frame on port 0 with pause_time equal to the value programmed in the port 0 fc tx timer value ($ port_index + 0x07) (xoff). 0x2 transmits a pause frame on port 1 with pause_time equal to the value programmed in the port 1 fc tx timer value ($ port_index + 0x07) (xoff). 0x3 transmits a pause frame on port 2 with pause_time equal to the value programmed in the port 2 fc tx timer value ($ port_index + 0x07) (xoff). page 74 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.1.3 mixed-mode operation the ixf1104 mac gives the user the option of configuring each port for 10/100 mbps half- duplex copper, 10/100/1000 mbps full-duplex copper, or 1000 mbps full-duplex fiber operation. this give s the ixf1104 mac the ability to support both co pper and fiber operation line-side interfaces operating at the same time within a single device. (refer to table 16, line side interface multiplexed balls , on page 59 .) the ixf1104 mac provides comple te flexibility in line-side con nectivity by offering rgmii, integrated serdes, and gmii. 5.1.3.1 configuration the memory maps ( table 59, mac control registers ($ port index + offset) , on page 149 through table 69, optical module registers ($ 0x799 - 0x79f) , on page 155 ) are logically split into the following two distinct regions: 0x4 transmits a pause frame on port 3 with pause_time equal to the value programmed in the port 3 fc tx timer value ($ port_index + 0x07) (xoff). 0x5 to 0x6 reserved. do not use these addresses. the tx pause control interface will not operate under these conditions. 0x7 transmits a pause frame on every port with pause_time equal to the value programmed in the fc tx timer value ($ port_index + 0x07) for each port (xoff). table 23 valid decodes for txpauseadd[2:0] (sheet 2 of 2) txpauseadd_2:0 operation of tx pause control interface figure 10 transmit pause control interface b3234-01 txpausefr txpauseadd0 txpauseadd1 txpauseadd2 this example shows the following conditions: strobe 1: port 0: transmit pause packet (xoff) strobe 2: all ports: transmit pause packet with pause_time = 0 (xon) strobe 3: port 3: transmit pause packet (xoff) page 75 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 ? per-port registers ? global registers to achieve a desired configuration for a given por t, the relevant per-port registers must be configured correctly by the user. the table 59 through table 69 also contain registers that affect the operation of all ports, su ch as the spi3 interface configuration. see section 8.0, register set , on page 148 for a complete description of ixf1104 mac configuration and status regi sters. the register maps ( table 59 through table 69 ) present a summary of important configuration registers. note: the initialization s equence provided in section 6.1, change port mode initialization sequence , on page 127 must be followed for proper configuration of the ixf1104 mac. 5.1.3.2 key configuration registers the following key registers select the operational mode of a given port: table 24 operational mode configuration registers register name register address description desired duplex ($ port_index + 0x02) 0x002 ? port 0 0x082 ? port 1 0x102 ? port 2 0x182 ? port 3 the table 71 on page 156 defines whether a port is to be configured for full-duplex or half-duplex operation. note: half-duplex operation is only valid for 10/100 speeds where the rgmii line interface has been selected. mac if mode and rgmii speed ($ port_index + 0x10) 0x010 ? port 0 0x090 ? port 1 0x110 ? port 2 0x190 ? port 3 the table 82 on page 160 determines the mac operational frequency and mode for a given port. note: set the table 152 on page 211 to 0x0 prior to any change in the register value. this ensures that a change in the mac clock frequency is controlled correctly. if the clock and interface mode change enable ports 0 - 3 ($0x794) is not used correctly, the ixf1104 mac may not be configured to the proper mode. port enable ($0x500) 0x500 bit 0 ? port 0 bit 1 ? port 1 bit 2 ? port 2 bit 3 ? port 3 each port enable ($0x500) bit relates to a port. set the appropriate bit to 0x1 to enable a port. this should be the last step in the configuration process for a port. interface mode ($0x501) 0x501 bit 0 ? port 0 bit 1 ? port 1 bit 2 ? port 2 bit 3 ? port 3 the interface mode ($0x501) selects whether a port operates with a copper (rgmii or gmii) line-side interface an integrated serdes fiber line-side interface. for copper operation for a given por t, set the relevant bit to 0x1. for fiber operation for a given port, set the relevant bit to 0x0. note: all ports are configured for fi ber operation in the ixf1104 mac default mode of operation. clock and interface mode change enable ports 0 - 3 ($0x794) 0x794 bit 0 ? port 0 bit 1 ? port 1 bit 2 ? port 2 bit 3 ? port 3 the clock and interface mode change enable ports 0 - 3 ($0x794) indicates to an internal clock generat or when to sample the new value of the mac if mode and rgmii speed ($ port_index + 0x10) and the interface mode ($0x501) (copper/fiber). when any of these two configurati on values are changed for a port, the corresponding bits must be kept in th is register under reset by writing 0x0 to the relevant bit. note: the initialization sequence provided in section 6.1, change port mode initialization sequence , on page 127 must be followed for proper configuration of the ixf1104 mac. page 76 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.1.4 fiber mode when the ixf1104 mac is configured for fiber mode, the tx data path from the mac is an internal 10-bit interface as described in the ieee 802.3z specif ication. it is connec ted directly to an internal serdes block for serialization/dese rialization and transmission/reception on the fiber medium to and from the link partner. the mac contains all of the pcs (8b/10b encoding and 10b/8b decoding) required to encode and decode the data. the mac also supports auto-negotiation per the ieee 802.3z specification via access to the tx config word ($ port_index + 0x17) , rx config word ($ port_index + 0x16) , and diverse config write ($ port_index + 0x18) . when configured for fiber mode, the full set of optical module interface control and status signals is presented through re-use of gmii signals on a per-port basis (see 4.5, multiplexed ball connections , on page 59 ). fiber mode supports only full-duplex gigabit operation. 5.1.4.1 fiber auto-negotiation auto-negotiation is performed by using the tx config word ($ port_index + 0x17) , rx config word ($ port_index + 0x16) , and diverse config write ($ port_index + 0x18) . when autoneg_enable ( diverse config write ($ port_index + 0x18) ) is set, the ixf1104 mac performs hardware-defined auto-negotiation with the tx config word ($ port_index + 0x17) used as an auto-negotiation advertisement ($ port index + 0x64) and the rx config word ($ port_index + 0x16) used as an auto-negotiation link partner base page ability ($ port index + 0x65) . note: while the mac supports auto-negotiation functions, the ixf1104 mac does not automatically configure the mac or other device blocks to be consistent with the auto- negotiation results. this configuration is done by t he user and system software. 5.1.4.2 determining if link is es tablished in auto-negotiation mode a valid link is established when the an_compl ete bit is set and the rx_sync bit reports that synchronization has occurred. both register bits are located in the rx config word ($ port_index + 0x16) . if the link goes down after auto-negotiation is completed, rx_sync indicates that a loss of synchronization occurred. the ixf1104 mac restarts auto-negotiation and attempts to reestablish a link. once a link is reestablished, the an_complete bit is set and the rx_sync bit shows that synchronization has occurred. to manually restart auto-negotiation, bit 5 of the section 90, diverse config write ($ port_index + 0x18) (an_enable) must be de-asserted, then re-asserted. 5.1.4.3 fiber forced mode the mac fiber operation can be forced to operate at 1000 mbps full-duplex without completion of the auto-negotiation function. in this mode, the mac rx path must achieve synchronization with the link partner. once achieved, the mac tx path is enabled to allow data transmission. this forced mode is limited to operation with a link partner that operates with a full-duplex link at 1000 mbps. page 77 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.1.4.4 determination of link establishment in forced mode when the ixf1104 mac is in forced mode operation, the section 88, rx config word ($ port_index + 0x16) bit 20 rx sync indicates when sync hronization occurs and a valid link establishes. note: the rx sync bit indicates a loss of syn chronization when the link is down. 5.1.5 copper mode in copper mode, the ixf1104 mac transmits data on the egress path of the rgmii or gmii interface, depending on t he port configuration defined by the user. the copper mac receives data on the ingress path of the rgmii or gmii interface, depending on the port configuration defined by the user. the rgmii interface supports operation at 10/100/1000 mbps when a full-duplex link is established, and supports 10/100 mbps when a half- duplex link is established. th e gmii interface only supports a 1000 mbps full-duplex link. 5.1.5.1 speed the copper mac supports 10 mbps, 100 mbps, and 1000 mbps. all required speed adjustments, clocks, etc., are supplied by th e mac. the operating speed of the mac is programmable through the mac if mode and rgmii speed ($ port_index + 0x10) (mac_if_mode). the ixf1104 mac speed setting must be programmed by the system software to match the speed of the attached phy for proper ixf1104 mac operation. note: when the ixf1104 mac is configured to use the gmii interface, the only mode of operation that is supported is 1000 mbps full-duplex. if 10/100 mbps operation is required in either full-duplex or half-duplex, the ixf1104 mac must be configured to use the rgmii interface. 5.1.5.2 duplex the mac supports full-duplex or half-duplex depending on the line-side interface that is configured by the mac if mode and rgmii speed ($ port_index + 0x10) (mac_if_mode). the duplex of the mac is set in the section table 71, desired duplex ($ port_index + 0x02) , on page 156 . the ixf1104 mac duplex setting must be programmed by the system software to match the atta ched phy duplex for proper ixf1104 mac operation. 5.1.5.3 copper auto-negotiation in the copper mac, auto-negotiation and all other controls of the phy devices are achieved through the mdio interface, and ar e independent of the mac controller. see section 5.5, mdio control and interface , on page 98 for further operation details. note: in copper mode, auto-n egotiation is accomplished by the attached phy, not the ixf1104 mac. thus, the ixf1104 mac does not automatically configure the mac or other blocks in the device to be consistent with attached phy auto-negotiation results. this must be accomplished by the user and system software. page 78 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.1.6 jumbo packet support the ixf1104 mac supports jumbo frames. the jumbo frame length is dependent on the application and the ixf1104 mac design is optimized for a 9.6 kb jumbo frame length. larger lengths can be programmed, but limited system performance may lead to data loss during certain flow-control conditions the value programmed into the max frame size (addr: port_index + 0x0f) determines the maximum length frame size the mac can re ceive or transmit without activating any error counters, and without truncation. the max frame size (addr: port_index + 0x0f) bits 13:0 set the frame length. the default value programmed into this register is 0x05ee (1518). the value is internally adjusted by +4 if the frame has a vlan tag. the overall programmable maximum is 0x3fff or 16383 bytes. the register should be programmed to 0x2667 for the 9.6 kb length jumbo frame, optimized for the ixf1104 mac. the rmon counters are also implemented for jumbo frame support as follows: 5.1.6.1 rx statistics ? rxoctetstotalok (addr: port_index + 0x20) ? rxpkts1519tomaxoctets (addr: port_index + 0x2b) ? rxfcserrors (addr: port_index + 0x2c) ? rxdataterror (addr: port_index = 0x02e) ? rxalignerrors (addr: port_index + 0x2f) ? rxlongerrors (addr: port_index + 0x30) ? rxjabbererrors (addr: port_index + 0x31) ? rxverylongerrors (addr: port_index + 0x34) 5.1.6.2 tx statistics ? octetstransmittedok (addr: port_index + 0x40) ? txpkts1519tomaxoctets (a ddr: port_index + 0x4b) ? txexcessivelengthdrop (addr: port_index + 0x53) ? txcrcerror (addr: port_index + 0x56) the ixf1104 mac checks the crc for all lega l-length jumbo fram es (frames between 1519 and the max frame size). on transmission, the mac can be programmed to append the crc to the frame or check the crc and increment the appropriate counter. on reception, the mac transmits these frames across the spi3 interface (jumbo frames above the setting in the section 128, rx fifo transfer threshold port 0 ($0x5b8) with a bad crc cannot be dropped and are sent across the spi3 interface). if the receive frame has a bad crc, the appropriate counter increm ents and the rxerr flag is asserted on the spi3 receive interface. jumbo frames also impact flow control. the maximum frame size needs to be taken into account when determining the fifo waterm arks. the current transmission must be completed before a pause frame is transmitte d (needed when the receiver fifo high watermark is exceeded). if the current tran smission is a jumbo frame, the delay may be significant and increase data loss due to insufficient available fifo space. page 79 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.1.6.3 loss-less flow control the ixf1104 mac supports loss-less flow co ntrol when the size of a jumbo packet is restricted to 9.6 k bytes. if this condition is met, the ixf1 104 mac has sufficient memory resources allocated to each mac port to ensure that, if both the ixf1104 mac and link partner are required to send pause packets simultaneously during jumbo packet transfers across a medium of five kilometers of fiber, no packet data should be lost due to fifo overflows. 5.1.7 packet buffer dimensions 5.1.7.1 tx and rx fifo operation 5.1.7.1.1 tx fifo the ixf1104 mac tx fifos are implemented with 10 kb for each channel. this provides enough space for at least one maximum size (10 kb) packet per-port storage and ensures that no under-run conditions occur, assuming that the sending device can supply data at the required data rate. a transfer to mac threshold parameter, which is user-programmable, determines when the fifo signals to the mac that it has data to send. this is configured for specific block sizes, and the user must ensure that an under-run does not occur. also, the threshold can be set above the maximum size of a normal ethernet packet. this causes the fifo to send only data to the mac when this threshold is exceeded or when the end-of-packet marker is received. this seco nd condition eliminat es the possibility of under-run, except when the controlling switch device fails. it can, however, cause idle times on the media. 5.1.7.1.2 rx fifo the ixf1104 mac rx fifos are provisioned so that each port has its own 32 kb of memory space. this is enough memory to ensure that there is never an over-run on any channel while transferring normal ethernet frame size data. the fifos automatically generate pause contro l frames to halt the link partner when the high watermark is reached and to restart the link partner when the data stored in the fifo falls below the low-watermark. the rx and tx fifos have been sized to support lossless flow control with 9.6 kb packets. the rx fifo has a programmable transfer threshold that sets the threshold at which packets beco me ?cut through? and starts transitioning to the spi3 interface before the eop is receiv ed. packets sizes below this threshold are treated as ?store and forward.? once a packet size exceeds the rx fifo transfer threshold, it can no longer be dropped by the rx fifo even if it is marked to be dropped by the mac. 5.1.8 rmon statistics support the ixf1104 mac supplies rmon statistics th rough the cpu interface. these statistics are available in the form of counter values th at can be accessed at specific addresses in the register maps ( table 59 through table 69 ). once read, these counters automatically reset and begin counting from zero. a separate set of rmon statistics is available for each mac device in the ixf1104 mac. implementation of the rmon statistics block is similar to the functionality provided by existing cortina switch and router products. this implementation allows the ixf1104 mac to provide all of the rmon statistics group as defined by rfc2819. the ixf1104 mac page 80 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 supports the rmon rfc2819 group 1 statistics counters. table 25 notes the differences and additional statistics registers supported by the ixf1104 mac that are outside the scope of the rmon rfc2819 document. table 25 rmon additional statistics (sheet 1 of 3) rmon ethernet statistics group 1 statistics type ixf1104 mac- equivalent statistics type definition of rmon versus ixf1104 mac documentation etherstatsindex integer 32 na na na etherstatsdatasource object identifier na na na etherstatsdropevents counter 32 rx number of frames removed/ tx number of frames removed counter 32 see table note 1 etherstatsoctets counter 32 rxoctetstotalok rxoctetsbad octetstransmittedok octetstransmittedbad counter 32 the ixf1104 mac has two counters for receive and transmit that use different naming conventions for the total octets and octets bad. these counters must be combined to meet the rmon definition for this statistic. etherstatspkts counter3 2 rxucpkts/txucpkts rxbcpkts/txbcpkts rxmcpkts/txmcpkts counter 32 the ixf1104 mac has three counters for the etherstatspkts that must be combined to give the total packets as defined by the rmon specification. etherstatsbroadcastpkts counter3 2 rxbcpkts/txbcpkts counter 32 same as rmon specification etherstatsmulticastpkts counter3 2 rxmcpkts/txmcpkts counter 32 see table note 2 note: the rmon specification requires that this is, ?t he total number of events where packets were dropped by the probe due to a lack of resources. this num ber is not necessarily the number of packets dropped; it is the number of times this condition is detected. the rx fifo overflow frame drop counter ports 0 - 3 ($0x594 ? 0x597) and tx fifo overflow frame drop counter ports 0 - 3 ($0x621 ? 0x624) in the ixf1104 mac support this and increm ent when either an rx fifo or tx fifo overflows. if any ixf1104 mac programm able packet filtering is enabled, the rx fifo errored frame drop counter ports 0 - 3 ($0x5a2 - 0x5a5) and tx fifo errored frame drop counter ports 0 - 3 ($0x625 ? 0x629) increment with every frame removed in addition to the existing frames counted due to fifo overflow. page 81 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 etherstatscrcalignerrors counter3 2 rxalignerrors rxfcserrors txcrcerror counter 32 the ixf1104 mac has two counters for the alignment and crc errors for the rx side only. the ixf1104 mac has a crc error counter for the tx side. etherstatsundersizedpkts counter3 2 rxrunterrors rxshorterrors rx statistics only counter 32 the ixf1104 mac has two counters, one for runt errors and one for shorterrors. etherstatsoversizepkts counter3 2 rxlongerrors txexcessivelength drop counter 32 same as rmon specification etherstatsfragments counter3 2 runterrors counter 32 same as rmon specification etherstatsjabbers counter3 2 jabbererrors counter 32 same as rmon specification etherstatscollisions counter3 2 txsinglecollision txmultiplecollision txlatecollision txtotalcollision counter 32 the txtotalcollision count value is equivalent to the rmon specification minus the txlatecollision etherstatspkts64octets counter3 2 rxpkts64octets/ txpkts64octets counter 32 same as rmon specification etherstatspkts65to127octets counter3 2 rxpkts65to127octets/ txpkts65to127octets counter 32 same a rmon specification etherstatspkts128to255octets counter3 2 rxpkts128to255octets/ txpkts128to255octets counter32 same a rmon specification etherstatspkts256to511octets counter3 2 rxpkts256to511octets/ txpkts256to511octets counter32 same a rmon specification etherstatspkts512to1023octets counter3 2 rxpkts512to1023octets/ txpkts512to1023octets counter32 same a rmon specification table 25 rmon additional statistics (sheet 2 of 3) rmon ethernet statistics group 1 statistics type ixf1104 mac- equivalent statistics type definition of rmon versus ixf1104 mac documentation note: the rmon specification requires that this is, ?t he total number of events where packets were dropped by the probe due to a lack of resources. this num ber is not necessarily the number of packets dropped; it is the number of times this condition is detected. the rx fifo overflow frame drop counter ports 0 - 3 ($0x594 ? 0x597) and tx fifo overflow frame drop counter ports 0 - 3 ($0x621 ? 0x624) in the ixf1104 mac support this and increm ent when either an rx fifo or tx fifo overflows. if any ixf1104 mac programm able packet filtering is enabled, the rx fifo errored frame drop counter ports 0 - 3 ($0x5a2 - 0x5a5) and tx fifo errored frame drop counter ports 0 - 3 ($0x625 ? 0x629) increment with every frame removed in addition to the existing frames counted due to fifo overflow. page 82 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.1.8.1 conventions the following conventions are used throughout the rmon management information base (mib) and its companion documents. ? good packets : error-free packets that have a va lid frame length. for example, on ethernet, good packets are error-free packets that are between 64 and 1518 octets long. they follow th e form defined in ieee 802.3, section 3.2. ? bad packets : bad packets are packets that have proper framing and recognized as packets, but contain errors within the packet or have an invalid length. for example, on ethernet, bad packets have a valid preamble and sfd, but have a bad crc, or are either shorter than 64 octets or longer than 1518 octets. 5.1.8.2 advantages the following lists additional ixf1104 ma c registers that support features not documented in rmon: ? mac (flow) control frames ? vlan tagged ? sequence errors ? symbol errors ? crc error these additional counters allow for differ entiation beyond standard rmon probes. note: in fiber mode, a packet transfer with an invalid 10-bit symbol does not always update the statistics registers correctly. ? behavior: the ixf1104 mac 8b10b decoder substitutes a valid code word octet in its place. the packet transfer is aborted and marked as bad. the new internal length of the packet is equal to the byte position where the invalid symbol was. no packet fragments are seen at the next packet transfer. etherstatspkts1023to1518 octets counter 32 rxpkts1023to1518octets/ txpkts1023to1518octets counter32 same as rmon specification etherstatowner owner string na na na etherstatsstatus entry status na na na table 25 rmon additional statistics (sheet 3 of 3) rmon ethernet statistics group 1 statistics type ixf1104 mac- equivalent statistics type definition of rmon versus ixf1104 mac documentation note: the rmon specification requires that this is, ?t he total number of events where packets were dropped by the probe due to a lack of resources. this num ber is not necessarily the number of packets dropped; it is the number of times this condition is detected. the rx fifo overflow frame drop counter ports 0 - 3 ($0x594 ? 0x597) and tx fifo overflow frame drop counter ports 0 - 3 ($0x621 ? 0x624) in the ixf1104 mac support this and increm ent when either an rx fifo or tx fifo overflows. if any ixf1104 mac programm able packet filtering is enabled, the rx fifo errored frame drop counter ports 0 - 3 ($0x5a2 - 0x5a5) and tx fifo errored frame drop counter ports 0 - 3 ($0x625 ? 0x629) increment with every frame removed in addition to the existing frames counted due to fifo overflow. page 83 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 ? issue: if the invalid 10-bit code is inserted in a byte position of 64 or greater, expected rx statistics are reported. however, if the inva lid code is inserted in a byte position of less than 64, expected rx statistics are not stored. 5.2 spi3 interface the ixf1104 mac spi3 interface is implemente d to the system packet interface level 3 (spi3) physical layer interface standard. the interface function allows the ixf1104 mac blocks to interface to higher-layer network processors or switch fabric. the ixf1104 mac transmit interface allows data flows from a network processor or switch fabric device to the ixf1104 mac. the receiv e interface allows data to flow from the ixf1104 mac to the network processor or switch fabric device. this interface receives and transmits data between the mac and the network processor with compliant spi3 interfaces. the spi3 interf ace operation is defined in the oif-spi3- 01.0 (available from the optical internet working fo rum [www.oiforum.com]). the oif specification defines operation for the transfer of data at data rates of up to 3.2 gbps when operating at a frequency of 104 mhz. the ixf1104 mac defines operation for the transfer of data at data rates of up to 4.256 gbps when operating at a maximum frequency of 133 mhz in mphy mode and 125 mhz in sphy mode. there is no guarantee of the number of by tes available since the size of packets is variable. an ixf1104 mac port-transmit packet available status is provided on signals dtpa, stpa or ptpa, indicati ng the tx fifo is nearly full. in the receive direction, rval indicates if valid data is available on the receive data bus and is defined so that data transfers can be aligned with packet boundaries. the spi3 interface supports the following two modes of operation: ? mphy or 32 bit mode (one 32-bit data bus) ? sphy or 4 x 8 mode (four individual 8-bit data buses) 5.2.1 mphy operation the mphy operation mode is selected when bit 21 of the section 146, spi3 transmit and global configuration ($0x700) is set to 0 and bit 7 of the spi3 receive configuration ($0x701) is set to 1. 5.2.1.1 data path the ixf1104 mac spi3 interface has a single 32-bit data path in the mphy configuration mode (see figure 13 ). the bus interface is point-to-poi nt (one output driving only one input load), so a 32-bit data bus would support only one ixf1104 mac. to support variable-length packets, the rmod[1:0]/tmod[1:0] signals are defined to specify valid bytes in the 32-bit data bus st ructure. each double-word must contain four valid bytes of packet data until the last do uble-word of the packet transfer, which is marked with the end of packet reop/teop signal. this last double-word of the transfer contains up to four valid bytes specif ied by the rmod[1:0]/tmod[1:0] signals. the ixf1104 mac port selection is perform ed using in-band addressing. in the transmit direction, the network processor device selects an ixf1104 mac port by sending the address on the tdat[1:0] bus marked with the tsx signal active and tenb signal inactive. all subsequent tdat[1:0] bus operat ions marked with the tsx signal inactive and the tenb active are packet data for the specified port. page 84 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 in the receive direction, th e ixf1104 mac specifies the selected port by sending the address on the rdat[1:0] bus marked with the rsx signal active and rval signal inactive. all subsequent rdat[1:0] bus oper ations marked with rsx inactive and rval active are packet data from the specified port. note: see table 17, spi3 mphy/sphy interface , on page 60 for a complete list of the mphy mode signals. the control signals with the po rt designator for port 0 are the only ones used in mphy mode and they apply to all 4 ports. table 3, spi3 interface signal descriptions , on page 40 provides a comprehensive list of spi3 signal descriptions. 5.2.1.2 spi3 rx round robin data transmission the ixf1104 mac uses a round-robin protocol to service each of the 4 ports dependent upon the enable status of the port and if ther e is data available to be taken from the rx fifo. the round robin order goes from port 0, por t 1, port 2, port 3, and back to port 0. a port is skipped and the next port is serviced if it has no available transmit data. the data transfer bursts are user-configurable burst lengths of 64, 128, or 256 bytes. the ixf1104 mac also has a configurable pause interval between data transfer bursts on the receive side of the interface. the rx spi3 burst leng ths and the pause interval can be set in the spi3 receive configuration ($0x701) ). 5.2.2 mphy logical timing the spi3 interface ac timing for mphy can be found in section 7.2, spi3 ac timing specifications , on page 133 . logical timing in the following diagrams illustrates all signals associated with mphy mode. 5.2.2.1 transmit timing in mphy mode a packet transmission starts with the tsx signal indicating port address information is on the data bus. the next clock cycle tenb and tsop indicate present data on the bus is the first word in the pack et and all subsequent clocks will contain valid data as long as tenb is active or until teop is asserted. data transmission can be temporally halted when tenb goes high then resumed when tenb is low. the valid bytes in the final word, during an active teop , are indicated by st ate of tmod [1:0]. page 85 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.2.2.2 receive timing a packet is received when rsx indicates port address information on the data bus followed by rsop to indicate the data bus contains the first word of a packet. all subsequent data is valid only while rval is high and until reop is asserted. receive data can be temporarily halted when renb is de-asserted and starts again on the second rising edge of rfclk following the assertio n of renb. rmod indicates the number of valid bytes in the last transf er when reop is asserted. figure 11 mphy transmit logical timing b3216-02 tfclk tenb tsop teop tmod [1:0] terr tsx tdat [31:0] tprty 0000 b0-b3 b4-b7 b48-b51 b44-b47 b52-b55 b60-b64 b56-b59 0001 b0-b3 b4-b7 1. applies to all transmit packet avai lable signals (stpa, ptpa, dtpa_0:3). figure 12 mphy receive logical timing page 86 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.2.2.3 clock rates in mphy mode, the tfclk and rfclk can be independent of each other. tfclk and rfclk should be common to the ixf1104 mac and the network processor. the ixf1104 mac requires a single clock source for the tr ansmit path and a single clock source for the receive path. to allow all four ixf1104 mac ports to operate at 1 gbps, the ixf1104 mac is designed to allow this interface to be overclocked. this allows operation for data transfer at data rates of up to 4.256 gbps when operating at an overclocked frequency of 133 mhz. note: mphy mode operates at a maximum clock frequency of 133 mhz (tfclk and rfclk). 5.2.2.4 parity the ixf1104 mac can be odd or even (the ixf1104 mac is odd by default) when calculating parity on the data bus. this can be changed to accommodate even parity if desired, and can be set for transmit and receive independently. the rx parity is set in bit 12 of the section 147, spi3 receive configuration ($0x701) and the tx parity is set in bit 4 of the section 146, spi3 transmit and global configuration ($0x700) . figure 13 mphy 32-bit interface b0660-02 tfclk tenb tdat[31:0] tprty terr tsx tsop teop network processor spi3 bus ixf1104 mphy mode transceiver tfclk tenb_0 tdat[31:0] tprty_0 tmod[1:0] tmod[1:0] rmod[1:0] rmod[1:0] terr_0 tsx tsop_0 teop_0 rfclk renb rdat[31:0] rprty rprty rval rerr rsx rsop reop rprty_0 rfclk renb_0 rdat[31:0] rval_0 rerr_0 rsx rsop_0 reop_0 dtpa_0:3 stpa ptpa tadr[1:0] dtpa_0:3 stpa ptpa tadr[1:0] transceiver transceiver transceiver line-side interface port 0 port 1 port 3 port 2 page 87 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.2.2.5 sphy mode the sphy operation mode is selected when bit 21 of the table 146, spi3 transmit and global configuration ($0x700) , on page 204 is set to 1. the sphy mode is the default operation for the ixf1104 mac spi3 interface. 5.2.2.5.1 data path the ixf1104 mac spi3 interface has four 8-bit data paths that can support four independent 8-bit point-to-point connections in sphy mode (see figure 16 ). since each mac port has its own dedicated 8-bit spi3 data bus, each port has it own status signal (unlike mphy). see the for a detailed list of all the signals refer to the spi3 pin multiplexing table.... furthermore since each port has it own dedicat ed bus the in band port addressing is not needed. the 8 bit data bus eliminates the need to have separate control signals determine the number of valid bytes on an eop.therefore tsx, rsx, tmod[1:0] rmod[1:0] are not used in sphy mode. note: see table 17, spi3 mphy/sphy interface , on page 60 for a complete list of the sphy mode signals. unlike mphy mode, each port has a dedicated control signal associated with each of the per-port 8-bit data buses. table 3, spi3 interface signal descriptions , on page 40 provides signal descriptions for all spi3 signals. 5.2.2.5.2 receive data transmission packets are transmitted on each port as they become available from the rx fifo. the burst length is determined by the setting of per port burst size and the b2b pause settings in the spi3 receive configuration ($0x701) . if the b2b pause setting is zero pause cycles inserted, then the entire packet will be burst without any pauses unless the network processor de-asserts renb. if the b2b_pause se tting calls for the insertion of two pause cycles on a port, these are inserted after each data burst for that port. the data bursts are user configurable for each port in the spi3 receive configuration ($0x701) . 5.2.2.6 sphy logical timing spi3 interface ac timing for sphy can be found in section 7.2, spi3 ac timing specifications , on page 133 . logical timing in the following diagrams illustrates all signals associated with sphy mode. sphy mode is si milar to mphy mode except the following signals are not used: ? tmod[1:0] ? rmod[1:0] ?tsx ?rsx ? address data appearing on the data bus 5.2.2.7 transmit timing (sphy) packet transmission starts when tenb and tsop indicate present data on the bus is the first word in the packet. all subsequent clocks will contain valid data as long as tenb is active or until teop is asserted. data transmission can be temporally halted when tenb goes high then resumed when tenb is low. page 88 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.2.2.8 receive timing (sphy) a packet is received when rsop is asserted to indicate the data bus contains the first word of the packet. all subsequent data is valid only while rval is high and until reop is asserted. receive data can be temporarily halted when renb is de-asserted and starts again on the second rising edge of rfclk following the assertion of renb. when reop is asserted rmod indicates the number of valid bytes in the last transfer. figure 14 sphy transmit logical timing b3249-02 tfclk tenb tsop teop terr tdat [7:0] tprty b0 b1 b60 b59 b61 b63 b62 b0 b1 b2 figure 15 sphy re ceive logical timing page 89 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.2.2.8.1 clock rates the tfclk and rfclk can be independent of each other in sphy mode operation. tfclk and rfclk should be common to a ll the network processor devices. the ixf1104 mac requires an individual single clock source for the device transmit path and a single clock sour ce for the device receive path. the ixf1104 mac allows this interface to be overclocked so that all four ixf1104 mac ports can operate at 1 gbps. this allows data transfer at data rates of up to 4.0 gbps when operating at an overclocked frequency of 125 mhz. note: sphy operates at a maximum frequency of 125 mhz. figure 16 sphy connection for two ixf1104 mac ports (8-bit interface) 45 .#6 .789: . .9;:9: .3.<9: .7339: . 9: .7 9: + .#6 .78= . .9;:= .3.<= .733= . = .7 = 3#6 3789: 3 .9;:9: 33.<9: 33.<= 3> #9: 37339: 3 9: 37 9: 3#6 378= 3 .9;:= 3> #= 3733= 3 = 37 = . 9: .#6 .789: . .9;:9: .3.<9: .7339: . 9: .7 9: 3#6 3789: 3 .9;:9: 33.<9: 33.<= 3> #9: 37339: 3 9: 37 9: . 9: . = .$ )? .#6 .78= . .9;:= .3.<= .733= . = .7 = 3#6 378= 3 .9;:= 3> #= 3733= 3 = 37 = . = .$ )? & & #)$) +$&0 #)$) +$&0 . . 39;: . . 39;: page 90 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.2.2.8.2 parity the ixf1104 mac can be odd or even (the ixf1104 mac defaults to odd) when calculating parity on the data bus. this can be changed to accommodate even parity if desired, and can be set for transmit and receive ports independently. the rx and tx parity sense bits have a direct relationship to the port parity in sphy mode. the per port rx parity is set in the spi3 receive configuration ($0x701) and the per port tx parity is set in the spi3 transmit and global configuration ($0x700) . 5.2.2.9 spi3 flow control the spi3 packet interface supports transmit and receive data transfers at clock rates independent of the line bit rate. as a result, the ixf1104 mac supports packet rate decoupling using internal fifos. these fifos are 10 kb per port in the transmit direction (egress from the ixf1104 mac to the line interfaces) and 32 kb per port in the receive direction (ingress to the ixf1104 mac from the line interfaces). control signals are provided to the network processor and the ixf1104 mac to allow either one to exercise flow control. since th e bus interface is point-to-point, the receive interface of the ixf1104 mac pushes data to the link-layer device. for the transmit interface, the packet available status granularity is byte-based. 5.2.2.9.1 rx spi3 flow control in the receive direction, when the ixf1104 mac has stored an end-of-packet (a complete small packet or the end of a larger packet) or some predefined number of bytes in its receive fifo, it sends the in-band address follo wed by fifo data to the link-layer device (in mphy mode). the data on the interface bus is marked with the valid signal (rval) asserted. the network processor device can pause the data flow by de-asserting the receive read enable (renb) signal. renb_0:3 renb_0:3 controls the flow of data from the ixf1104 mac rx fifos. in sphy mode, there is a dedicated renb for each port. in mphy mode, renb_0 is used as the global signal covering all ports. when renb is samp led low, the network processor can accept data. a read is performed from the rx fi fo and the rdat, rprty, rmod[1:0], rsop, reop, rerr, rsx, and rval signals are updated on the following rising edge of rfclk. renb can be asserted high by the network processo r at any time if it is unable to accept any more data. when the renb is sampled high by the ixf1104 mac, a read of the rx fifo is not performed, and the rdat, rprty, rmod[1:0], rsop, reop, rerr, rsx and rval signals remain unchanged on the following rising edge of rfclk. 5.2.2.9.2 tx spi3 flow control in the transmit direction, when the ixf1104 mac has space for some predefined number of bytes in its transmit fifo, it informs the network processor device by asserting one of the transmit packet available (tpa) signals. the network processor device writes the in- band address followed by packet data to the ixf1104 mac using an enable signal (tenb). the network processor device monitors the tpa signals for a high-to-low transition, which indicates that th e transmit fifo is almost full (the number of bytes left in the fifo is user-selectable by setting the tx fifo high watermark ports 0 - 3 ($0x600 ? 0x603) , and suspends data transfer to avoid an overflow. the network processor device can pause the data flow by de-asserting the enable signal (tenb). page 91 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 the ixf1104 mac provides the following three types of tpa signals: ? dedicated per port direct transmit packet available (dtpa) ? selected-phy transmit packet available (stpa), which is based on the current in- band port address in mphy mode. ? polled-phy transmit packet available (ptp a), which provides fifo information on the port selected by the tadr[1:0] signals. the following three tpa signals (dtpa_0:3, stpa, and ptpa) provide flow control based on the programmable tx fifo high and low watermarks. refer to table 132, tx fifo high watermark ports 0 - 3 ($0x600 ? 0x603) , on page 195 and table 133, tx fifo low watermark register ports 0 - 3 ($0x60a ? 0x60d) , on page 196 for more information. dtpa_0:3: a direct status indication for the tx fifos of ports [0:3]. when dtpa is high, it indicates the amount of data in the tx fifo is below the tx fifo high watermark. when the high watermark is crossed, dtpa transitions low to indicate the tx fifo is almost full. it stays low until the amount data in the tx fifo goes back below the tx fifo low watermark. at this point, dtpa transitions high to indicate the programmed number of bytes are now available for data transfers. dtpa_0:3 is updated on the rising edge of the tfclk. stpa: stpa provides tx fifo status for the curr ently selected port in mphy mode. when high, stpa indicates that the amount of data in the tx fifo for the port selected, specified by the latest in-band address, is below the tx fifo high watermark. when the high watermark is crossed, stpa transitions low to indicate the tx fifo is almost full. it stays low until the amount of data in the tx fifo goes back below the tx fifo low watermark. at this point, stpa transitions high to indicate the programmed number of bytes are now available for data transfers. the port reported by stpa is updated on the rising edge of tfclk after tsx is sampled as asserted. stpa is updated on the rising edge of tfclk. note: stpa is only used when the ixf1104 mac is configured for mphy mode of operation. ptpa: ptpa provides status of the tx fifo based on the port selected by the tadr[1:0] address bus. when high, ptpa indicates that the amount of da ta in the tx fifo for the port selected is below the tx fifo high watermark. when the high watermark is crossed, ptpa transitions low to indicate the tx fifo is almost full. it st ays low until the amount of data in the tx fifo goes back below the tx fifo low watermark. ptpa then transitions high to indicate the programmed number of bytes are now available for data transfers. the port reported by ptpa is updated on th e rising edge of tfclk after the tadr{1:0] port address is sampled. ptpa is updated on the rising edge of tfclk. page 92 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.2.3 pre-pending function the ixf1104 mac implements a pre-pending feat ure to allow 1518-byte ethernet packets to be pre-padded with two additional bytes of data so that the packet becomes low-word aligned. the 2-byte pre-pend value is all zeros and is inserted before the destination address of the packet being pre-pended. th is value is fixed and cannot be changed. this function is enabled by writing the appropriate data to the rx fifo padding and crc strip enable ($0x5b3) for each port. a standard 1518-byte ethernet packet occupies 379 long words (four bytes) with two additional bytes left over (1518/4 = 379.5). to eliminate the memory-management problems for a network processor or switch fabric, the two remaining bytes are dealt with by the addition of two bytes to the start of a packet. this results in a standard 1518-byte ethernet packet received by the ixf1104 ma c being forwarded to the higher-layer device as a 380-long-word packet. the upper-layer device is responsible for stripping the additional two bytes. this feature was added to the ixf1104 mac to assist in the design of higher-layer memory management. the addition of the two ex tra bytes is not the default operation of the ixf1104 mac and must be enabled by the user. the default operation of the ixf1104 mac spi3 receive interface forwards data exac tly as it is received by the ixf1104 mac line interface. 5.3 gigabit media independent interface (gmii) the ixf1104 mac supports a su bset of the gmii interface standard as defined in ieee 802.3 2000 edition for 1 gbps operation only. th is subset is limited to operation at 1000 mbps full-duplex. the gmii interface operates as a source synch ronous interface only and does not accept a txc clock provided by a phy device when operating at 10/100 mbps speeds. note: the rgmii interface must be used for applications that require 10/100/1000 mbps operation. the ixf1104 mac does not support 10/100 mbps copper phy devices that are implemented using the mii interface. note: mii operation is not supported by the ixf1104 mac. the user can select gmii, rgmii, or optica l module/serdes functionality on a per-port basis. this mode of operation is cont rolled through a configuration register. while ieee 802.3 specifies 3. 3 v operation of gmii devi ces, most phys use 2.5 v signaling. the ixf1104 mac provides a 2.5 v drive and is 3.3 v-tolerant on inputs. page 93 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.3.1 gmii signal multiplexing the gmii balls are reassigned when using the rgmii mode or fiber mode. table 16, line side interface multiplexed balls , on page 59 specifies the multiplexi ng of gmii balls in these modes. see section 5.1.3, mixed-mode operation , on page 74 for proper configuration of the ixf1104 mac in gmii mode. 5.3.2 gmii interface signal definition table 26, gmii interface si gnal definitions , on page 94 provides the gmii interface signal definitions. for information on 1000base-t gmii transmit and receive timing diagrams and tables, please refer to table 49, gmii 1000base-t transm it signal parameters , on page 138 , figure 37, 1000base-t transmit interface timing , on page 138 , figure 38, 1000base-t receive interface timing , on page 138 , and table 50, gmii 1000base-t receive signal parameters , on page 139 figure 17 mac gmii interconnect txc_3:0 tx_en_3:0 tx_er_3:0 rxc_3:0 txd[7:0]_0 txd[7:0]_3 txd[7:0]_2 txd[7:0]_1 rx_en_3:0 rx_er_3:0 rxd[7:0]_0 rxd[7:0]_3 rxd[7:0]_2 rxd[7:0]_1 col_3:0 crs_3:0 ixf1104 media access controller txc_3:0 tx_en_3:0 tx_er_3:0 txd[7:0]_0 txd[7:0]_3 txd[7:0]_2 txd[7:0]_1 rxc_3:0 rx_en_3:0 rx_er_3:0 rxd[7:0]_0 rxd[7:0]_3 rxd[7:0]_2 rxd[7:0]_1 col_3:0 crs_3:0 quad phy device b3203-02 page 94 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 26 gmii interface signal definitions ixf1104 mac signal gmii standard signal source description txc_0 txc_1 txc_2 txc_3 gtx_clk ixf1104 mac transmit reference clock: 125 mhz for gigabit operation. mii operation for 10/100 mbps operation is not supported. txd[7:0]_0 txd[7:0]_1 txd[7:0]_2 txd[7:0]_3 txd[7:0] ixf1104 mac transmit data bus: width of this synchronous output bus varies with the speed/mode of operation. in 1000 mbps mode, all 8 bits are used. tx_en_0 tx_en_1 tx_en_2 tx_en_3 tx_en ixf1104 mac transmit enable: synchronous input that indicates valid data is being driven on the txd[7:0] data bus. tx_er_0 tx_er_1 tx_er_2 tx_er_3 tx_er ixf1104 mac transmit error: synchronous input to phy causes the transmission of error symbols in 1000 mbps links. rxc_0 rxc_1 rxc_2 rxc_3 rx_clk phy receive clock: continuous reference clock is 125 mhz +/? 100 ppm. rxd[7:0]_0 rxd[7:0]_1 rxd[7:0]_2 rxd[7:0]_3 rxd<3:0> phy receive data bus: width of the bus varies with the speed and mode of operation. in 1000 mbps mode, all 8 bits are driven by the phy device. note: mii operation at 10/100 mbps is not supported. rx_dv_0 rx_dv_1 rx_dv_2 rx_dv_3 rx_dv phy receive data valid: this signal is asserted when valid data is present on the corresponding rxd bus. rx_er_0 rx_er_1 rx_er_2 rx_er_3 rx_er phy receive error: in 1000 mbps mode, asserted when error symbols or carrier extension symbols are received. always synchronous to rx_clk. crs_0 crs_1 crs_2 crs_3 crs phy carrier sense: asserted when valid activity is detected at the line- side interface. col_0 col_1 col_2 col_3 col phy collision: asserted when a collision is detected and remains asserted for the duration of the collision event. in full- duplex mode, the phy shoul d force this signal low. page 95 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.4 reduced gigabit media in dependent inte rface (rgmii) the ixf1104 mac supports the rgmii interface standard as defined in the rgmii version 1.2 specification. the rgmii in terface is an alternative to the ieee 802.3u mii interface. the rgmii interfac e is intended as an alternative to the ieee 802.3u mii and the ieee 802.3z gmii. the principle objective of the rg mii is to reduce the number of balls (from a maximum of 28 balls to 12 balls) required to interconnect the mac and the phy. this reduction is both cost-effective and technolo gy-independent. to accomplish this objective, the data paths and all associated control signals are reduced, control signals are multiplexed together, and both edges of the clock are used. ? 1000 mbps operation ? clocks operate at 125 mhz ? 100 mbps operation ? cl ocks operate at 25 mhz ? 10 mbps operation ? cloc ks operate at 2.5 mhz. note: the ixf1104 mac rgmii interface is multiple xed with signals from the gmii interface. see table 16, line side interface multiplexed balls , on page 59 for detailed information. 5.4.1 multiplexing of data and control multiplexing of data an d control info rmation is achieved by ut ilizing both edges of the reference clocks and sending the lower four bits on the rising edge and the upper four bits on the falling edge. control si gnals are multiplexed into a single clock cycle using the same technique. for further information on timing parameters, see figure 36, rgmii interface timing , on page 137 and table 48, rgmii interface timing parameters , on page 137 . figure 18 rgmii interface txc_3:0 tx_en_3:0 tx_er_3:0 rxc_3:0 txd[7:0]_0 txd[7:0]_3 txd[7:0]_2 txd[7:0]_1 rx_en_3:0 rx_er_3:0 rxd[7:0]_0 rxd[7:0]_3 rxd[7:0]_2 rxd[7:0]_1 col_3:0 crs_3:0 ixf1104 media access controller txc_3:0 tx_en_3:0 tx_er_3:0 txd[7:0]_0 txd[7:0]_3 txd[7:0]_2 txd[7:0]_1 rxc_3:0 rx_en_3:0 rx_er_3:0 rxd[7:0]_0 rxd[7:0]_3 rxd[7:0]_2 rxd[7:0]_1 col_3:0 crs_3:0 quad phy device b3203-02 page 96 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.4.2 timing specifics the ixf1104 mac rgmii complies wit h rgmii rev1.2a requirements. table 27 provides the timing specifics. 5.4.3 tx_er and rx_er coding to reduce interface power, the transmit error condition (tx_er) and the receive error condition (rx_er) are encoded on the rgmii interface to minimize transitions during normal network operation (refer to table 28 on page 96 for the encoding method). ta b l e 27 provides signal definitions for rgmii. the value of rgmii_tx_er and rgmii_tx_en are valid at the rising edge of the clock while tx_er is presented on the falling edge of the clock. rx_er coding behaves in the same way (see table 28 , figure 19 , and figure 20 ). table 27 rgmii signal definitions ixf1104 mac signal rgmii standard signal source description txc_0:3 txc mac depending on speed, the transmit reference clock is 125 mhz, 25 mhz, or 2.5 mhz +/? 50ppm. td[3:0]_ n td<3:0> mac contains register bits 3:0 on the rising edge of txc and register bits 7:4 on the falling edge of txc. tx_en tx_ctl mac txen is on the leading edge of txc. tx_en xor tx_er is on the falling edge of txc. rxc_0:3 rxc phy continuous reference clock is 125 mhz, 25 mhz, or 2.5 mhz +/? 50 ppm. rd[3:0]_ n rd<3:0> phy contains register bits 3:0 on the leading edge of rxc and register bits 7:4 on the trailing edge of rxc. rx_dv rx_ctl phy rx_dv is on the leading edge of rxc. rx_dv or rxerr is the falling edge of rxc. table 28 tx_er and rx_e r coding description condition description receiving valid frame, no errors rx_dv = true logic high on rising edge of rxc rx_er = false logic high on the falling edge of rxc receiving valid frame, with errors rx_dv = true logic high on rising edge of rxc rx_er = true logic low on the falling edge of rxc receiving invalid frame (or no frame) rx_dv = false logic low on rising edge of rxc rx_er = false logic low on the falling edge of rxc transmitting valid frame, no errors tx_en = true logic high on rising edge of txc tx_er =false logic high on the falling edge of txc transmitting valid frame with errors tx_en = true logic high on rising edge of txc tx_er = true logic low on the falling edge of txc transmitting invalid frame (or no frame) tx_en = false logic low on rising edge of txc tx_er = false logic low on the falling edge of txc note: refer to figure 19 for tx_ctl behavior, and figure 20 for rx_ctl behavior. page 97 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 figure 19 tx_ctl behavior b0616-02 txc_0:3 (at transmitter) td[3:0]_0:3 tx_ctl_0:3 end-of-frame td[3:0] td[7:4] tx_en=true tx_er=false tx_en=false tx_er=false txc_0:3 (at transmitter) td[3:0]_0:3 tx_ctl _0:3 end-of-frame td[3:0] td[7:4] tx_en=true tx_er=false tx_en=false tx_er=false valid frame frame with error figure 20 rx_ctl behavior b3237-01 rxc_0:3 (at phy) rd[3:0]_0:3 rx_ctl_0:3 end-of-frame rd[3:0] rd[7:4] rx_dv=true rx_er=false rx_dv=false rx_er=false rxc_0:3 (at phy) rd[3:0]_0:3 rx_ctl _0:3 end-of-frame rd[3:0] rd[7:4] rx_dv=true rx_er=true rx_dv=false rx_er=false valid frame frame with error page 98 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.4.3.1 in-band status carrier sense (crs) is generated by the phy when a packet is received from the network interface. crs is indicated when: ? rxdv = true. ? rxdv = false, rxerr = true, and a valu e of ff exists on the rxd[7:0] bits simultaneously. ? carrier extend, carrier extend error, or false carrier occurs (please reference the hewlett-packard* version 1.2a rg mii specification for details.). carrier extend and carrier extend error are applicable to giga bit speeds only. collision is determined at the mac by the assertion of txen being true while either crs or rxdv are true. the phy will not assert crs as a result of txen being true. 5.4.4 10/100 mbps functionality the rgmii interface implements the 10/100 mbps ethernet media independent interface (mii) by reducing the clock rate to 25 mhz for 100 mbps operation and 2.5 mhz for 10 mbps. the txc is generated by the mac and the rxc is generated by the phy. during packet reception, the rxc is stretched on either the positive or negative pulse to accommodate transition from the free-running clock to a data-synchronous clock domain. when the speed of the phy changes, a simila r stretching of the positive or negative pulses is allowed. no glit ching of the clocks is allowed during speed transitions. this interface operates at 10 mbps and 100 mbps speeds in the same manner as 1000 mbps speed, although the dat a may be duplicated on the fa lling edge of th e appropriate clock. the mac holds tx_ctl low until it is operating at the same speed as the phy. note: the ixf1104 mac does not support 10/100 mbps operation when configured in gmii mode 5.5 mdio control and interface the ixf1104 mac support s the ieee 802.3 mii management interface, also known as the management data input/output (mdio) interface. this interface allows the ixf1104 mac to monitor and control each of the phy devices that are connected to the four ports of ixf1104 mac when those ports are in copper mode. the mdio master interface block is impl emented once in the ixf1104 mac. the mdio interface block contains the logic through wh ich the user accesses the registers in phy devices connected to the mdio/mdc interface, which is controlled by each port. the mdio master interface block supports the management frame format, specified by ieee 802.3, clause 22.2.4.5. th is block also supports sing le mdi access through the cpu interface and an autoscan mode. autoscan allows the ixf1104 mac mdio master to read all 32 registers of the per-port copper phys and store the contents in the ixf1104 mac. this provides external-cpu-ready access to the phy register contents through a single cpu read without the latency of waiting on the low-speed serial mdio data bus for each register access. scan of a single register with low-frequency operation takes approximately 25.6 s. scan of a 32-register block takes approximately 820 s, or 3.3 ms for all four ports. autoscan data is not valid until approximately 19.2 s after enabling scan. these numbers scale by 7/50 for high-frequency operation. page 99 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.5.1 mdio address the 5-bit phy address for the mdio transactions can be set in the mdio single command ($0x680) . bits 5:2 of the phy address are fixe d to a value of 0. bits 1 and 0 are programmable in bits 9 and 8 of mdio single command ($0x680) . 5.5.2 mdio register descriptions for complete information on the mdi registers, refer to the table 142, mdio single command ($0x680) , on page 202 , table 143, mdio single read and write data ($0x681) , on page 203 , table 144, autoscan phy addre ss enable ($0x682) , on page 203 , and table 145, mdio control ($0x683) , on page 204 . 5.5.3 clear when done the mdi command register bit, in the mdio single command ($0x680) , clears upon command completion and is set by the user to start the requested single mdio read or write operation. this bit is cleared automatically upon operation completion. 5.5.4 mdc generation the mdc clock is used for the mdio/mdc inte rface. the frequency of the mdc clock is selectable by setting bit 0, mdc speed, in an ixf1104 mac configuration register (see table 145, mdio control ($0x683) , on page 204 ). 5.5.4.1 mdc high-frequency operation the high-frequency mdc is 18 mhz, derived from the 125-mhz system clock by dividing the frequency by 7. the duty cycle is as follows: ? mdc high duration: 3 x (1/125 mhz) = 3 x 8 ns = 24 ns ? mdc low duration: 4 x (1/125 mhz) = 4 x 8 ns = 32 ns ? mdc runs continuously after reset refer to figure 40, mdc high-speed operation timing , on page 140 for the high- frequency mdc timing diagram. 5.5.4.2 mdc low-frequency operation the low-frequency mdc is 2.5 mhz, which is derived from the 125-mhz system clock by dividing the frequency by 50. the duty cycle is as follows: ? mdc high duration: 25 x (1/125 mhz) = 25 x 8 ns = 200 ns ? mdc low duration: 25 x (1/125 mhz) = 25 x 8 ns = 200 ns ? mdc runs continuously after reset refer to figure 41, mdc low-speed operation timing , on page 140 for the low frequency mdc timing diagram. page 100 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.5.5 management frames the management interface serializes the exter nal register access information into the format specified by ieee 802. 3, section 22.2.4.5 (see figure 21 ). 5.5.6 single mdi command operation the management data interface is accessed through the mdio single command ($0x680) and the mdio single read and write data ($0x681) . a single management frame is sent by setting register 0, bit 20 to logic 1, and is automatically cleared when the frame is completed. the write data is first set up in register 1, bits 15:0 for write operation. register 0 is initialized with the appropriate control informatio n (start, op code, etc.) and register 0, bit 20 is set to logic 1. register 0, bit 20 is reset to logic 0 when the frame is complete. the steps are identical for read operation except that in register 1, bits 15:0, the data is ignored. the data received from the mdio is read by the cpu interface from register 1, bits 31:16. 5.5.7 mdi state machine the mdi state machine sequences the information sent to it by the mdio control registers and keeps track of the current sequence bit c ount, enabling or disabling the mdio driver output (see figure 22 . figure 21 management frame structure (single-frame format) preamble 32 bits start 2 bits op code 2 bits phy addr 5 bits turnaround 2 bits data 16 bits first bit transmitte d last bit transmitte d reg addr 5 bits page 101 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 figure 22 mdi state idle preamble go = 1 cnt = 32 cnt < 32 start bits cnt = 2 cnt < 2 cnt > 32 cnt > 2 cnt > 2 op code phy addr cnt = 2 cnt < 2 cnt > 5 cnt < 5 reg addr cnt = 5 cnt = 5 cnt < 5 cnt > 5 turn around cnt > 2 cnt < 2 cnt = 2 data cnt < 16 cnt > 16 cnt = 16 and go = 1 or (cnt = 16 and go = 0) mdoe = 0 mdo = 0 mdc_en = 0 mdoe = 1 mdo = 1 mdc_en = 1 mdoe = 1 mdo = reg_bit_st(cnt) mdc_en = 1 mdoe = 1 mdo = reg_bit_op(cnt) mdc_en = 0 mdoe = 1 mdo = reg_bit_pa(cnt) mdc_en = 1 mdoe = 1 mdo = reg_bit_ra(cnt) mdc_en = 1 mdoe = wr_op mdo = reg_bit_wo(cnt) mdc_en = 1 mdoe = wr_op mdo = data(cnt) mdc_en = 1 page 102 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.5.8 autoscan operation the autoscan function allows the 32 registers in each external phy (up to four) to be stored internally in the ixf1104 mac. autosc an is enabled by setting bit 1 of the mdi control register. when enabled, autoscan runs continuously, reading each phy register. when a phy register access is instigated through the cpu inte rface, the current autoscan register read is completed before the cpu register access starts. upon completion of the cpu-induced access, the autoscan functionality restarts from the last autoscan register access. the autoscan phy address enable ($0x682) determines which phy addresses are being occupied for each ixf1104 mac port. the least significant bit (lsb) that is set in the register is port 0, the next significant bit that is set is assumed to be port 1, and so on. if more than four bits are set, the bits beyond the fourth bit are ignored. if less than four bits are set, the round-robin process returns to the port identified by the lsb being set. 5.6 serdes interface the ixf1104 mac integrates four integrated se rializer/deserializer (serdes) devices that allow direct connection to optical modules and remove the requirement for external serdes devices. this increa ses integration, which reduces the size of the pcb area required to implement this function, re duces total power, reduces silicon and manufacturing costs, and improves reliability. each serdes interface is identical and fully compliant with the relevant i eee 802.3 specifications, includ ing auto-negotiation. each port is also compliant with and supports the requirements of the small form factor pluggable (sfp) multi-source agreement (msa), see section 5.7, optical module interface , on page 106 . the following sections describe the operations supported by each interface, the configurable options, and the register bits that control these options. a full list of the register addresses and full bit definitions are found in the register maps ( table 59 through table 69 ). 5.6.1 features the serdes cores are designed to operate in point-to-point data transmission applications. while the core can be used acro ss various media types, such as pcb or backplanes, it is conf igured specifically fo r use in 1000base-x ethern et fiber applications in the ixf1104 mac. the following features are supported. ? 10-bit data path, which connects to the output/input of the 8b/10b encoder/decoder pcs that resides in the mac controller ? data frequency of 1.25 ghz ? low power: <200 mw per serdes port ? asynchronous clock data recovery 5.6.2 functional description the serdes transmit interface sends serializ ed data at 1.25 ghz. the interface is differential with two signals for transmit opera tion. the transmit interface is designed to operate in a 100 differential environment and all the terminations are included on the device. the outputs are high-speed serdes and are capable of operating in either an ac- or dc-coupled environment. ac coupling is recommended for this interface to ensure that the correct input bias current is supplied at the receiver. page 103 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 the serdes receive interface receives seria lized data at 1.25 ghz. the interface is differential with two signals for the receive operation. the equalizer receives a differential signal that is equalized for the assumed media channel. the serdes transmit and receive interfaces are designed to operate within a 100 differential environment and all terminations are included on the device. the serd es is capable of operating in either ac- or dc-coupled environments. 5.6.2.1 transmitter operational overview the transmit section of the ixf1104 mac has to serialize the ten bit interface (tbi) data from the ixf1104 mac mac section and outputs th is data at 1.25 ghz differential signal levels. the 1.25 ghz differential serdes sign als are compliant with the small form factor pluggable (sfp) multi-source agreement (msa). the transmitter section takes the contents of the data register within the mac and synchronously transfers the data out, ten bits at a time ? least significant bit (lsb) first, followed by the next most significant bit (msb). when these ten bits have been serialized and transmitted, the next word of 10-bit data from the mac is ready to be serialized for transmission. the data is transmitted by the high-speed cu rrent mode differential serdes output stage using an internal 1.25 ghz clock generated from the 125 mhz clock input. 5.6.2.2 transmitter programmable driver-power levels the ixf1104 mac serdes core has programmable transmitter power levels to enhance usability in any given application.the serd es registers are prog rammable to allow adjustment of the transmit core driver output power. when driving a 100 differential terminated network, these out put power settings effectively establish the differential voltage swings at the driver output. the tx driver power level ports 0 - 3 ($0x784) allows the selection of four discrete power settings. the selected power setting of these inputs is applied to each of the transmit core drivers on a per-port basis. table 29, serdes driver tx power levels lists the normalized power settings of the transmit drivers as a fu nction of the driver po wer control inputs. the normalized current setting is 10 ma, which co rresponds to the normalized power setting of 1.0. this is the default setting of the ixf1104 mac serdes interface. other values listed in the normalized driver power se tting column are multiples of 10 ma. for example, with inputs at 1110, the driver power is the following: equation 1 .5 x 10 ma = 5 ma. table 29 serdes driver tx power levels drvpwrx[3] drvpwrx[2] drvpwrx[1] drvpwrx[0] normalized driver power setting driver power 0011 1.3313.3 ma 1011 2.020 ma 1101 1.010 ma 1110 0.5 5 ma note: all other values are reserved. page 104 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.6.2.3 receiver operational overview the receiver structure performs clock and data recovery (cdr) on the incoming serial data stream. the quality of this operation is a dominant factor for the bit error rate (ber) system performance. feed forward and feedback controls are combined in one receiver architecture for enhanced performance. the data is over-sampled and a digital circuit detects the edge position in the data stream. a signal is not generated if an edge is not found. a feedback loop takes care of low-frequency jitter phenomenon of unlimited amplitude, while a feed forward section s uppresses high-frequency jitter having limited amplitude. the static edge position is held at a constant position in the over-sampled by a constant adjustment of the sampling ph ases with the early and late signals. 5.6.2.4 selective power-down the ixf1104 mac offers the abilit y to selectively powe r-down any of the serdes tx or rx ports that are not being used. this is done via section table 150, tx and rx power-down ($0x787) , on page 210 . 5.6.2.5 receiver jitter tolerance the serdes receiver architecture is designed to track frequency mismatch, recover phase, and is tolerant of low-frequency data jitter. figure 23 specifies the serdes core receiver sinusoidal jitte r tracking capabilities. page 105 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.6.2.6 transmit jitter the serdes core total transmit jitter, incl uding contributions from the intermediate frequency pll, is comprised of the following two components: ? a deterministic component attributed to the serdes core?s architectural characteristics ? a random component attributed to random thermal noise effects since the thermal noise component is random and statistical in nature, the serdes core total transmit jitter must be sp ecified as a function of ber. 5.6.2.7 receive jitter the serdes core total receiv er jitter, including contributions from the intermediate frequency pll, is comprised of the following two components: ? a deterministic component attributed to the serdes core architectural characteristics ? a random component attributed to random thermal noise effects. figure 23 serdes rece iver jitter tolerance note: ui = unit interval. b0745-02 10-1 0 10+1 10 0 10 1 10 2 10 3 10 4 10 5 10 6 10 7 frequency sinusoidal jitter mask peak-to-peak amplitude (ui) 16 ui 375 hz 16 ui 22.5836 khz 8.5 ui 1.9195 mhz 0.1 ui page 106 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.7 optical module interface this section describes the connection of the ixf1104 mac ports to an optical module interface and details the minimal connections that are supported for correct operation. the registers used for write control and read status information are documented. the optical module interface allows the ixf1104 mac a seamless connection to the small form factor optical modules (sfp) that form the system?s physical media connection, eliminating the need for any fpgas or cpus to process data. all required optical module inform ation is available to the system cpu through the ixf1104 mac cpu interface, leading to a more integrated, reliable, and cost-effective system. the ixf1104 mac supports all the functions requ ired for the small form factor pluggable multi-source agreement (msa). there are specific mechanical and electrical requirements for the size, form factor, and connections supported on all optical modul e interfaces. there are also specific requirements for each optical module interface that supports a particular media requirement or interface configuration. these requirements are detailed in the relevant specifications or manufacturers? datasheets.ixf1104 mac 5.7.1 ixf1104 mac-supported opti cal module interface signals to describe the optical module interface oper ation, three supported signal subgroups are required, allowing a more explicit definition of each function and implementation. the three subgroups are as follows: ? high-speed serial interface ? low-speed status signaling interface ? i2c module configuration interface table 30 provides descriptions for ixf1104 mac-to-sfp optical module connection signals. table 30 ixf1104 mac-to-sfp opti cal module interface connections ixf1104 mac signal names sfp signal names description notes tx_p_0:3 td+ transmit data, differential lvds output from the ixf1104 mac tx_n_0:3 td- transmit data, differential lvds output from the ixf1104 mac rx_p_0:3 rd+ receive data, differential lvds input to the ixf1104 mac rx_n_0:3 rd- receive data, differential lvds input to the ixf1104 mac i 2 c_clk mod-def1 i 2 c_clk output from the ixf1104 mac (scl) output from the ixf1104 mac i 2 c_data_0:3 mod-def2 i 2 c_data i/o (sda) input/output mod_def_0:3 mod-def0 mod_def_0 is ttl low level during normal operation. input to the ixf1104 mac tx_disable_0:3 tx disable transmitter disable, logic high, open collector compatible output from the ixf1104 mac tx_fault_0:3 tx fault transmitter fault, logic high, open collector compatible input to the ixf1104 mac rx_los_0:3 los receiver loss-of-si gnal, logic high, open collector compatible input to the ixf1104 mac page 107 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.7.2 functional descriptions 5.7.2.1 high-speed serial interface these signals are responsible for transf er of the actual data at 1.25 gbps. table 41, dc specifications , on page 131 shows the data is 8b/10b encoded and transmitted differentially. the following signals are required to implement the high-speed serial interface: ? tx_p_0:3 ? tx_n_0:3 ? rx_p_0:3 ?rx_n_0:3 5.7.2.2 low-speed status signaling interface the following low-speed signals indicate the state of the line through the optical module interface: ? mod_def_0:3 ?tx_fault_0:3 ? rx_los_0:3 ? tx_disable_0:3 ? mod_def_int ?tx_fault_int ? rx_los_int 5.7.2.2.1 mod_def_0:3 mod_def_0:3 are direct inputs to the ixf1104 mac and are pulled to a logic low level during normal operation, indicating that a module is present for each channel respectively. if a module is not present, a logic high is rece ived, which is achieved by an external pull- up resistor at the ixf1104 mac device pad. the status of each bit (one for each port) is found in bits [3:0] of the table 153 on page 212 ). any change in the state of these bits causes a logic low level on the mod_def_int output if this operation is enabled. 5.7.2.2.2 tx_fault_0:3 tx_fault_0:3 are inputs to the ixf1104 mac. these signals are pulled to a logic low level by the optical module during normal operation. a logic low level on these signals indicates no fault condition exists. if a fault is present, a logic high is received through the use of an external pull-up resistor at the ixf1104 mac pad. the status of each bit (one for each port ) can be found in bits [13:10] of the table 153 on page 212 . any change in the state of these bits causes a logic low level on the tx_fault_int output if this operation is enabled. page 108 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.7.2.2.3 rx_los_0:3 rx_los_0:3 are inputs to the ixf1104 mac. these signals are pulled to a logic low level by the optical module during normal operation, which indicates that no loss-of-signal exists. if a loss-of-signal occu rs, a logic high is received on these inputs through the use of an external pull-up resistor at the ixf1104 mac device pad. the status of each bit (one for each port) is found in optical module status ports 0-3 ($0x799) bits [23:20]. any change in the state of these bits causes a logic low level on the rx_los_int output if this operation is enabled. 5.7.2.2.4 tx_disable_0:3 tx_disable_0:3 are outputs from the ixf1104 mac. these si gnals are driven to a logic low level by the ixf1104 mac during normal operation. this indicates that the optical module transmitter is enabled. if the optical module transmitter is disabled, this signal is switched to a logic high level. on the ixf1104 mac, these outputs are open drain types and pulled up by the 4.7 k to 10 k pull-up resist or at the optical module interface. each of these signals is controlled throug h bits 3:0 respectively of the optical module control ports 0 - 3 ($0x79a) . 5.7.2.2.5 mod_def_int mod_def_int is a single output , open-drain type signal and is active low. a change in state of any mod_def_0:3 inputs causes this signal to switch low and remain in this state until a read of the optical module status ports 0-3 ($0x799) . the signal then returns to an inactive state. 5.7.2.2.6 tx_fault_int tx_fault_int is a single output, open-drain ty pe signal and is active low. a change in state of any tx_fault_0:3 inputs causes this signal to switch low and remain in this state until a read of the optical module status ports 0-3 ($0x799) . the signal then returns to an inactive state. 5.7.2.2.7 rx_los_int rx_los_int is a single output, open-drain type signal and is active low. a change in state of any of the rx_los_3:0 inputs causes th is signal to switch low and remain in this state until a read of the optical module status ports 0-3 ($0x799) has taken place. the signal returns to an inactive state. note: mod_def_int, tx_fault_int, and rx_los_int are open-drain type outputs. with the three signals on the device, the system can decide which optical module status ports 0-3 ($0x799) bits to look at to identify the interrup t condition source port. however, this is achieved at the expense of the three device signals. 5.7.3 i2c module configuration interface the i2c interface is supported on sfp optical modules. details of the operation are found in the sfp multi-source agre ement, which details the contents of the registers and addresses accessible on a given optical module interface supporting this interface. the sfp msa identifies up to 512 8-bit registers that are accessible in each optical module. the optical module interface is read-only and supports either sequential or random access to the 8-bit parameters. the maximum clock rate of the interface is 100 khz. all address-select signals on the internal e2prom are tied low to give a device address equal to zero (00h). page 109 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 several phy vendors may offer copper/cat5-based sfp optical compliant modules. to program the internal configuration regist ers of these modules, the ixf1104 mac i 2 c interface needs to provide the capabilit y to write data to the sfp modules. the ixf1104 mac i 2 c interface is designed to allow individual writes of byte-wide data to the sfp. the specific interface in the ixf1104 mac suppor ts only a subset of the full i2c interface, and only the features required to support t he optical module interfaces are implemented. this leads to the following support features. ?single i 2 c_clk pin connected to all optical modules and implemented to save unnecessary signals use. ? four per-port i 2 c_data signals (i2c data[3:0]) are required because of the optical module requirement that all modules must be addressed as 00h. ? the interface has both read and write functionality. ? due to the single internal optical module controller, only one optical module may be accessed at any one time. each access contains a single register read. since these register accesses will most likely be done during power-up or discovery of a new module, these restrictions should not affect normal operation. ? the i 2 c interface supports byte write accesses to the full address range. note: the i 2 c interface only supports random single-byte reads and does not guarantee coherency when reading two-byte registers. 5.7.3.1 i 2 c control and data registers in the ixf1104 mac, the entire i2c interf ace is controlled thro ugh the following two registers: ? section table 155, i 2 c control ports 0 - 3 ($0x79b) , on page 214 ? section table 156, i 2 c data ports 0 - 3 ($0x79f) , on page 214 these registers can be programmed by system software using the cpu interface. 5.7.3.2 i 2 c read operation to perform a read operation using the i 2 c interface, use the following sequence: 1. initialize the control register by setting the following values: a. enable the i 2 c controller by setting bit [25] to 0x1. b. initiate the i 2 c transfer by setting bit [24] of the control register to 0x1. c. select the port by using bits [17:16]. d. select the read mode of operation by setting bit [15] to 0x1. e. select the device id by setting bits [14:11]. f. select the register address by setting bits [10:0]. 2. set the device id field to 0xa and the regi ster address (bits 10:8) to 0x0 to access the fiber module serial e2prom. setting the de vice id field to 0xa and the register address [10:8] to 0x0 permits read-only access. 3. set the device id field to 0xa and the regi ster address [10:8] between the values of 0x1 and 0x7 to access the phy registers. 4. poll the read_valid field, bit 20. the read data is available when this bit is set to 0x1. page 110 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 figure 24 shows an 8-bit read access. note: the user software ensures the order of the contiguous accesses required to read the high and low bytes of 16-bit-wide phy registers. note: only one optical module i2c access sequence can be run at any given time. if a second write is carried out to the i 2 c control ports 0 - 3 ($0x79b) and i 2 c data ports 0 - 3 ($0x79f) before a result is returned for the previous write, the data for t he first write is lost. an internal state machine completes the opti cal module interface register access for the first write. it attempts to place the data in the dataread field and checks to see if the writecommand bit is 00h. if it is not 00h, it discards the data and signals the i2c access state machine to begin a new cycle using the data from the second write. 5.7.3.3 i 2 c write operation the following sequence provides an example of writing data to register address 0xff for port 3: 1. program the i 2 c control ports 0 - 3 ($0x79b) with the followi ng information: a. enable the i 2 c block by setting register bit 25 to 0x1. b. set the port to be accessed by setting register bits 17:16 to 0x3. c. select a write access by setting register bit 15 to 0x0. d. set the device id register bits 14:11 to ah (atmel compatible). e. set the 11-bit register address (register bits 10:0) to 0ffh. f. enable the i 2 c controller by setting register bit 2 to 0x1. g. initiate the i 2 c transfer by setting register bit 24 to 0x1. all other bits in this register should be set to 0x0. this data is written into the i 2 c control ports 0 - 3 ($0x79b) in a single cycle via the cpu interface. 2. when this register is written and the i 2 c start bit is at a logic 1, the i 2 c access state machine examines the port address select and enables the i 2 c_data_0:3 output for the selected port. 3. the state machines uses the data in the device id and register address fields to build the data frame to be sent to the optical module figure 24 i 2 c random read transaction device address device address word address i 2 c_data li ne dummy wri te (* = don' t care bi t f or 1k) start s t a r t r e a d s t a r t w r i t e s t o p m s b m s b m s b l s b r / w l s b data n l s b a c k n o a c k a c k * page 111 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 4. the i 2 c_data_write_fsm internal state machine takes over the task of transferring the actual data between t he ixf1104 mac and the selected optical module (refer to the details in section 5.7.3.4, i2c protocol specifics , on page 111 ). 5. the i 2 c_data_write_fsm internal state machine uses the data from the write_data field bits [23:16] of the table 156 on page 214 and sets the write_complete regist er bit 22 of the i 2 c control ports 0 - 3 ($0x79b) to 0x1 to signify that the write access is complete. 6. the data is written through the cpu interf ace. the cpu must poll the write_complete bit until it is set to 0x1. it is safe to request a new access only when this bit is set. note: only one optical module i 2 c access sequence can be run at any given time. the data for the first write is lost if a second write is carried out to the i 2 c control ports 0 - 3 ($0x79b) before a result is returned for the previous wr ite. make sure write complete = 0x1 before starting the next write sequence to ensure that no data is lost. 5.7.3.4 i2c protocol specifics section 5.7.3.4 describes the ixf1104 mac i2c protocol behavior, which is controlled by an internal state machine. specific protocol states are defined bel ow, with an additional description of the hardware signals used on the interface. the serial clock line (i 2 c_clk) is an output from the ixf1104 mac. the serial data is synchronous with this clock and is driven of f the rising edge by the ixf1104 mac and off the falling edge by the optical modu le. the ixf1104 mac has only one i 2 c_clk line that drives all of the optical modules. i 2 c_clk runs continuously when enabled (i2c enable = 01h0). the serial data (i 2 c_data_3:0) signals (one per port) are bi-directional for serial data transfer. these signals are open drain. 5.7.3.5 port protocol operation 5.7.3.6 clock and data transitions the i 2 c_data is normally pulled high wit h an extra device. data on the i 2 c_data pin changes only during the i 2 c_clk low time periods (see figure 25 ). data changes during i 2 c_clk high periods indicate a start or stop condition. figure 25 data validity timing data stable data stable data change i 2 c_data i 2 c_clk page 112 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.7.3.6.1 start condition a high-to-low transition of i 2 c_data, with i 2 c_clk high, is a start condition that must precede any other command (see figure 26 ). 5.7.3.6.2 stop condition a low-to-high transition of the i 2 c_data with i 2 c_clk high is a stop condition. after a read sequence, the stop command places the e2prom and the optical module in a standby power mode (see figure 26 ). 5.7.3.6.3 acknowledge all addresses and data words are serially transmitted to and from the optical module in 8- bit words. the optical module e2prom sends a zero to acknowledge that it has received each word, which happens during the ninth clock cycle (see figure 27 ). 5.7.3.6.4 memory reset after an interruption in protocol, power loss, or system re set, any 2-wire optical module can be reset by following three steps: 1. clock up to 9 cycles figure 26 start and stop definition timing start stop i 2 c_data i 2 c_data figure 27 acknowledge timing start acknowledge i 2 c_data data in data out page 113 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 2. wait for i 2 c_data high in each cycle while i 2 c_clk is high 3. initiate a start condition. 5.7.3.6.5 device addressing all e2proms in sfp optical module devices require an 8-bit device address word following a start condition to enable the chip to read or write. the device address word consists of a mandatory one, zero sequence fo r the four most-significant bits. this is common to all devices. the next three bits are the a2, a1, and a0 device address bits that are tied to zero in an optical module. the ei ghth bit of the device address is the read/ write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon comparison of the device address, the optical module outputs a zero. if a comparison is not made, the optical module e2prom returns to a standby state. 5.7.3.6.6 random read operation a random read requires a ?dummy? byte/write sequence to load the data word address. the ?dummy? write is achieved by first sendi ng the device address word with the read/ write bit cleared to low, which signals a write operation. the optical module acknowledges receipt of the device address word. the ixf1104 mac sends the data word address, which is again acknowledged by the optical module. the ixf1104 mac generates another start condition. this completes the ?dummy? write and sets the optical module e2prom pointers to the desired location. the ixf1104 mac initiates a current address read by sending a device address with the read/write bit set high. the optical module acknowledges the device address and serially clocks out the data word. the ix f1104 mac does not respond with a zero but generates a stop condition (see figure 28 ). 5.8 led interface the ixf1104 mac uses a serial interface, cons isting of three signals, to provide led data to some form of external driver. this provid es the data for 12 separate direct drive leds and allows three leds per mac port. there are two modes of operation, each with its own separate led decode mapping. modes of operation and leds are detailed in the following sections. figure 28 random read device address devi ce address word address i 2 c_dat a li ne dummy wri te (* = don' t care bi t f or 1k) start s t a r t r e a d s t a r t w r i t e s t o p m s b m s b m s b l s b r / w l s b data n l s b a c k n o a c k a c k * page 114 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.8.1 modes of operation there are two modes of operation: mode 0 and mode 1. mode selection is accomplished by using the led_sel_mode bit. this bit is gl obally selected and controls the operation of all ports (see table 109, led control ($0x509) , on page 183 ). mode 0: (led_sel_m ode = 0 [default]): this mode selects oper ations compatible with the sgs thompson m5450 led display driver device. this device converts the serial data stream, output by the ixf1104 mac, into 30 direct-drive led outputs. although the led interface is capabl e of driving all 30 leds, only twel ve will be driven in the four-port ixf1104 mac, three leds per port. mode 1: (led_sel_mode = 1): this mode is used with standard ttl (74ls599) or hcmos (74hc599) octal shift registers with latches, providing the most general and cost- effective implementation of the serial data stream conversion. in addition to these physical modes of operatio n, there are two types of specific led data decodes available for fiber and copper modes. this option is a global selection and controls the operation of all ports (see table 109, led control ($0x509) , on page 183 ). 5.8.2 led interface signal description the ixf1104 mac led interface consists of three output signal signals that are 2.5 v cmos level pads. table 31 provides led signal names, pin numbers, and descriptions. 5.8.3 mode 0: detailed operation note: please refer to the sgs thompson* m5450 datasheet for device-operation information. the operation of the led interface in mode 0 is based on a 36-bit counter loop. the data for each led is placed in turn on the seri al data line and clocked out by the led_clk. figure 29 shows the basic timing relationship and re lative positioning in the data stream of each bit. figure 29 shows the 36 clocks that are output on the led_clk pin. the data is changed on the falling edge of the clock and is valid fo r almost the entire cl ock cycle. this ensures that the data is valid during the rising edge of the led_clk, which clocks the data into the m5450 device. the actual data shown in figure 29 consists of a chain of 36 bits, 12 of which are valid led data. the 36-bit data chain is built up as follows: table 31 led interface signal descriptions pin name pin # pin description led_clk k24 this signal is an output that provides a continuous clock synchronous to the serial data stream output on the led_ data pin. this clock has a maximum speed of 720 hz. the behavior of this signal remains constant in all modes of operation. led_data m22 this signal provides the data, in various formats, as a serial bit stream. the data must be valid on the rising edge of the led_clk signal. in mode 0, the data presented on this pin is true (logic 1 = high). in mode 1, the data presented on this pin is inverted (logic 1 = low). led_latch l22 this is an output pin, and the signal is used only in mode 1 as the latch enable for the shift register chain. this signal is not used in mode 0, and should be left unconnected. page 115 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 when implemented on the board with the m5450 device, the led data bit 1 appears on output bit 3 of the m5450 and the led data bit 2 appears on output bit 4, etc. this means that output bits 1, 2, and 15 through 35 will never have valid data and should not be used. 5.8.4 mode 1: detailed operation note: please refer to generic specifications for 7 4ls/hc599 for information on device operation. the operation of the led interface in mode 1 is based on a 36-bit counter loop. the data for each led is placed in turn on the seri al data line and clocked out by the led_clk. figure 30 on page 116 shows the basic timing relationship and relative positioning in the data stream of each bit. figure 30 on page 116 shows the 36 clocks which are output on the led_clk pin. the data is changed on the falling edge of the clock and is valid for the almost the entire clock cycle. this ensures that the dat a is valid during the rising edge of the led_clk, which clocks the data into the shift register chain devices. the led_latch signal is required in mode 1, and latches the data shifted into the shift register chain into the output latches of the 74hc599 device. figure 30 shows that the led_latch signal is active high during the low period on the 35th led_clk cycle. this avoids any possibility of trying to latch da ta as it is shifting through the register. figure 29 mode 0 timing 1 22 23 24 25 26 27 28 29 30 135 34 33 32 31 30 29 28 27 26 25 234 led_clk led_data led_latch table 32 mode 0 clock cycle to data bit relationship led_clk cycle led_data name led_data description 1start bit this bit synchronizes the m5450 device to expect 35 bits of data to follow. 2:3 pad bits these bits are used only as fillers in the data stream to extend the length from the actual 12-bit led data to the required 18-bit frame length. these bits should always be a logic 0. 4:15 led data 1-12 these bits are the actual data transmitted to the m5450 device. the decode for each individual bit in each mode is defined in table 34 on page 117 . the data is true. logic 1 (led on) = high 36:38 pad bits these bits are used as fillers in the data stream to extend the length from the actual 30-bit led data to the required 36-bit frame length. these bits should always be a logic 0. page 116 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 when this operation mode is implemented on a bo ard with a shift register chain containing three 74hc599 devices, the led data bit 1 is outp ut on shift register bit 1, and so on up the chain. only shift register bits 31 and 32 do not contain valid data. the actual data shown in figure 30 consists of a 36-bit chain, of which 12 bits are valid led data. the 36-bit data chain is built up as shown in figure 30 . note: the led_data signal is now inverted from the state in mode 0. 5.8.5 power-on, reset, initialization the led interface is disabled at power-on or reset. the system soft ware controller must enable the led interface. the internal state ma chines and output signals are held in reset until the full cortina systems ? ixf1104 4-port gigabit ethernet media access controller device configuration is comple ted. this is done by setting the led_enable bit to a logic 1 (see table 109, led control ($0x509) , on page 183 ). the power-on default for this bit is logic 0. 5.8.6 led data decodes the data transmitted on the led_data line is determined by programming the global operation mode as either fiber or copper. table 34 shows the data decode of the data for both fiber and copper macs. figure 30 mode 1 timing 1 22 23 24 25 26 27 28 29 30 135 34 33 32 31 30 29 28 27 26 25 234 led_clk led_data led_latch table 33 mode 1 clock cycle to data bit relationship led_clk cycle led_data name led_data description 1start bit this bit has no meaning in mode 1 operation and is shifted out of the 16-stage shift register chain before the led_latch signal is asserted. 2:3 pad bits these bits have no meaning in mode 1 operation and are shifted out of the 16-stage shift register chain before the led_latch signal is asserted. 4:15 led data 1-12 these bits are the actual data to be transmitted to the 16-stage shift register chain. the decode for each bit in each mode is defined in table 34 on page 117 . the data is invertd. logic 1 (led on) = low. 36:38 pad bits these bits have no meaning in mode 1 operation and are latched into positions 31 and 32 in the shif t register chain. these bits are not considered as valid data and should be ignored. they should always be a logic 0 = high. page 117 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 note: the data decode of the led bits is independent of the physical mode selection. 5.8.6.1 led signaling behavior operation in each mode for the decoded led data in table 34 is detailed in table 35 and table 36 . 5.8.6.1.1 fiber led behavior table 34 led_data# decodes led_data# mac port # fiber de signation copper designation 1 0 rx led?amber link led?amber 2 rx led?green link led?green 3 tx led?green activity led?green 4 1 rx led?amber link led?amber 5 rx led?green link led?green 6 tx led?green activity led?green 7 2 rx led?amber link led?amber 8 rx led?green link led?green 9 tx led?green activity led?green 10 3 rx led?amber link led?amber 11 rx led?green link led?green 12 tx led?green activity led?green table 35 led behavior (fiber mode) type status description rxled off synchronization occurs but no packets are received and the section 105, link led enable ($0x502) is not set. amber on rx synchronization has not occurred or no optical signal exists. amber blinking the port has remote fault and the section 105, link led enable ($0x502) is not set (based on remote fault bit setting received in rx_config word). green on rx synchronization occurs and the section 105, link led enable ($0x502) bit is set. green blinking rx synchronization occurs and the port is receiving data. txled off the port is not transmitting data or the section 105, link led enable ($0x502) is not set. green blinking the port is transmitting data and the section 105, link led enable ($0x502) bit is set note: table 35 assumes the port is enabled in the section 103, port enable ($0x500) and the leds are enabled in the section 109, led control ($0x509) . if a port is not enabled, al l the leds for that port will be off. if the leds are not enabled, all of the leds will be off. page 118 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.8.6.1.2 copper led behavior 5.9 cpu interface the cpu interface block provides access to r egisters and statistics in the ixf1104 mac. the interface is asynchronous externally an d operates within the 125 mhz clock domain internally. the interface prov ides access to the following: ? receive statistics registers ? transmit statistics registers ? receive fifo registers ? transmit fifo registers ? global configuration and control registers ? mac_0 to mac_3 registers the cpu interface width can be configured with the two strap signals (upx_width[1:0]) to operate as an 8-bit, 16-bit, or 32-bit bus. all internal accesses to registers are 32-bit (4, 2, or 1 data cycles respectively are required to fully access a register). when operating in 8-bit or 16-bit mode, read data for bytes [3:1] is strobed into read holding registers when byte [0] is read. subsequent reads of bytes {1, 2, 3} in byte mode or of bytes {2,3} in 16-bit mode are supplied from the holding register independent of the upper address bits. on write accesses in 8-bit mode, the data of bytes {0, 1, 2} is similarly captured in internal write holding registers and the complete 32-bit write is committed when byte[3] is written to the ixf1104 mac. when writing in 16-b it mode, bytes [1:0] are captured, and the double-word is committed when bytes [3:2] are written. the complete address for write is ignored (except for the write which causes the commit operation). table 36 led behavior (copper mode) type status description link led off port does not have a remote fault and section table 109, led control ($0x509) , on page 183 bit is not set. amber on port has an rgmii rxerr condition detected and section table 109, led control ($0x509) , on page 183 bit is set amber blinking port has a remote fault and section table 111, led fault disable ($0x50b) , on page 184 is not set. green on section table 109, led control ($0x509) , on page 183 bit is set and port does not have an rgmii rxerr error or remote fault condition present. activity led - green off port is not transmitting and receiving data. blinking section table 109, led control ($0x509) , on page 183 set: port is transmitting and/or receiving. section table 109, led control ($0x509) , on page 183 not set: port is receiving data. note: table 34, led_data# decodes assumes the port is enabled in the section table 103, port enable ($0x500) , on page 181 and the leds are enabled in the section table 109, led control ($0x509) , on page 183 . if a port is not enabled, all the leds for that port are off. if the leds are not enabled, all of the leds are off. page 119 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.9.1 functional description 5.9.1.1 read access read access involves the following: ? detect assertion of asynchronous read control signal and latch address ? generate internal read strobe ? drive valid data onto processor bus ? assert asynchronous ready signal for required length of time comment: shows the timing of the asynchronous interface for read access. 5.9.1.2 write access write process involves the following: ? detect assertion of asynchronous write control signal and latch address ? detect de-assertion of asynchronous write control signal and latch data ? generate internal write strobe ? assert asynchronous ready signal for required length of time figure 31 shows the timing of the asynchro nous interface for write accesses. comment: read timing diagram - asynchronous interface t cas t cah t crr t cdrs t cdrh t cdrd t crh upx_add[10:0] upx_rdn upx_csn upx_data[31:0] upx_rdyn b5103-01 page 120 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.9.1.3 cpu timing parameters for information on the cpu interface read an d write cycle ac timing parameters, refer to figure 46, cpu interface read cycle ac timing , on page 143 , figure 47, cpu interface write cycle ac timing , on page 144 , and table 54, cpu interface write cycle ac signal parameters , on page 144 . 5.9.2 endian the endian of the cpu interface may be changed to allow connection of various cpus to the cortina systems ? ixf1104 4-port gigabit ethernet media access controller. the endian selection is determined by setting the endian bit in the cpu interface ($0x508) . the following describes endianness control: ? there is a byte swapper between the inter nal 32-bit bus and the external 32-bit bus. ? in 8-bit or 16-bit mode operation, the byte packer/byte unpacker holding registers sink and source data just like the 32-bit external bus in 32-bit mode. ? the cpu interface ($0x508) selects big-endian or little-endian mode. ? the byte swapper causes the behavior seen in table 37 for accessing a register with data bits data[31:0]. figure 31 write timing diagram - asynchronous interface t cas t cah t cwl t cdws t cdwd t cyd t cwh upx_add[12:0] upx_wrn upx_csn upx_data[31:0] upx_rdyn t cdwh page 121 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.10 tap interface (jtag) the ixf1104 mac includes an ieee 1149.1 comp liant test access port (tap) interface used during boundary scan testing. the interfac e consists of the following five signals: ? tdi ? serial data input ? tms ? test mode select ? tclk ? tap clock ? trst_l ? active low asynch ronous reset for the tap ? tdo ? serial data output tdi and tms require external pull-up resist ors to float the signals high per the ieee 1149.1 specification. pull-ups are recommended on tck and tdo. for normal operation, trst_l can be pulled low, permanently disabling the jtag interface. if the jtag interface is used, the tap controller must be reset as described in section 5.10.1, tap state machine , on page 121 and returned to a logic high. 5.10.1 tap state machine the tap signals drive a tap controller, which implements the 16-state state machine specified by the ieee 1149.1 specificat ion. following power-up, the tap controller must be reset by one of following two mechanisms: ? asynchronous reset ? synchronous reset asynchronous reset is achieved by pulsing or holding trst_l low. synchronous reset is achieved by clocking tclk with five clock pu lses while tms is held or floats high. this ensures that the boundary scan cells do not block the pin to core connections in the ixf1104 mac. table 37 byte swapper behavior upx_badd [1:0] little endian big endian 32-bit 16-bit 8-bit 1 32-bit 16-bit 8-bit 1 upx_data_ [31:0] upx_data [15:0] upx_data [7:0] upx_data [31:0] upx_data [15:0] upx_data [7:0] 00 [31:0] [15:0] [7:0] [7:0] [15:8] [23:16 [31:24] [7:0] [15:8] [7:0] 01 ? ? [15:8] ? ? [15:8] 10 ? [31:16] [23:16] ? [23:16] [31:24] [23:16] 11 ? ? [31:24] ? ? [31:24] 1. in 8-bit mode, data is output in little endian format regardless of the ixf1104 mac endian setting. page 122 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.10.2 instruction register and supported instructions the instruction register is a 4-bit register that enacts the boundary scan instructions. after the state machine resets, the default instruction is idcode. the decode logic in the tap controller selects the appropriate data register and configures the boundary scan cells for the current instruction. table 38 shows the supported boundary-scan instructions. 5.10.3 id register the id register is a 32-bit register. the idco de instruction connects this register between tdi and tdo. see table 112, jtag id ($0x50c) , on page 185 for detailed information. 5.10.4 boundary scan register the boundary scan register is a shift regi ster made up of all the boundary scan cells associated with the device signals. the number , type, and order of the boundary scan cells are specified in the ixf1104 mac bsd l file. the extest and sample instructions connect this register between tdi and tdo. 5.10.5 bypass register the bypass register is a 1-bit register th at bypasses the ixf1104 mac to reduce the jtag chain length when accessing other devi ces on the chain besides the ixf1104 mac. the bypass, highz, and clamp instructions connect this register between tdi and tdo. 5.11 loopback modes the ixf1104 mac provides two loopback modes for device diagnostic testing when it has been integrated into a user system. a lin e-side loopback allows the line-side receive interface to be looped back to the transmit line-side interface. a spi3 loopback mode allows the spi3 transmit in terface to be looped back to the spi3 receive interface. the ixf1104 mac line-side and spi3 loopback modes are effective diagnostic tools for validation of system level connect ivity and interface compatibility. in loopback-mode operation, the data path is in ternally redirected to allow for the data flow return path. redirection requires the data path to circumvent resources that are required during normal traffic flow. for example, while operating in spi3 loopback mode, the data path does not pass through the mac or tx fifo and those resource features are not used. the result is a possible degradation of throughput performance and statistical data accuracy. cortina recommends that loopba ck modes be used for diagnostic purposes only. table 38 instruction register description instruction code description data register bypass 1111 1-bit bypass bypass extest 0000 external test boundary scan sample 0001 sample boundary boundary scan idcode 0110 id code inspection id highz 0101 float boundary bypass clamp 0111 clamp boundary bypass page 123 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.11.1 spi3 interface loopback to provide a diagnostic loopback feature on the spi3 interface, it is possible to configure the ixf1104 mac to loop back any data written to the ixf1104 mac through the spi3 transmit interface back to the spi3 receive in terface. this is accomplished using the data path shown in figure 32 . note: loopback packets also appear on the line side tx interface. note: there is a restriction when using this loopba ck mode. at least one clock cycle is required between a teop assertion and a tsop assert ion. this is required when the pre-pend feature of the receive fifo is enabled to allow the addition of the extra two bytes to the data sent on the transmit interface. wher e the pre-pend feature has not been enabled, data can be sent back-to-back on the transmit spi3 interface with tsop following teop on the next cycle. to configure the ixf1104 mac to use the spi3 loopback mode, the rx fifo spi3 loopback enable for ports 0 - 3 ($0x5b2) must be configured. each ixf1104 mac port has a unique bit in this register designated to control loopback. it is possible to have individual ports in a loopback mode while other ports continue to operate in a normal mode. 5.11.2 line side interface loopback to provide a diagnostic loopback feature on the line-side interfaces, the ixf1104 mac can be configured to loop back any data received by the ixf1104 mac through one of the line interfaces back to the corresponding transm it line interface. this is done by using the data path shown in figure 33 . the line-side interface can be either serdes, rgmii or gmii. please note that it is not possible to lo op one line-side interface back to a different one (for example, rx serdes looped back to transmit rgmii). figure 32 spi3 interface loopback path spi3 interface block tx rx line side interface mac tx fifo rx fifo b3229-01 spi3 internal loopback page 124 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 when the ixf1104 mac is configured in this loopback mode, all of the mac functions and features are available, including flow control and pause-packet generation. to configure the ixf1104 mac to use the line-side loopback mode, the loop rx data to tx fifo (line-side loopback) ports 0 - 3 ($0x61f) must be configured. each ixf1104 mac port has a unique bit in this register de signated to control the loopback. it is possible to have individual ports in a loopback mode while other ports continue to operate in a normal mode. note: line side interface loopback packets also appear at the spi3 interface. 5.12 clocks the ixf1104 mac system interface has severa l reference clocks, including the following: ? spi3 data path input clocks ? rgmii input and output clocks ? mdio output clock ? jtag input clock ?i 2 c clock ? led output clock. this section details the unique clock source requirements. 5.12.1 system interf ace reference clocks the following system interface cloc k is required by the ixf1104 mac: ? clk125 figure 33 line side interface loopback path rx fifo spi3 interface block tx rx line side interface mac tx fifo b3230-01 line side internal loopback page 125 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.12.1.1 clk125 the system interface clock, which supplies th e clock to the majority of the internal circuitry, is the 125 mhz clock. the sour ce of this clock must meet the following specifications: ? 2.5 v cmos drive ? +/- 50 ppm ? maximum duty cycle distortion 40/60 5.12.2 spi3 receive and transmit clocks the ixf1104 mac transmit clock requirements include the following: ? 3.3 v lvttl drive ? +/- 50 ppm ? maximum frequency of 133 mhz in mphy mode ? maximum frequency of 125 mhz in sphy mode ? maximum duty cycle distortion 45/55 the ixf1104 mac meets the following specifications for the receive clock: ? 3.3 v lvttl drive ? +/- 50 ppm ? maximum frequency of 133 mhz in mphy mode ? maximum frequency of 125 mhz in sphy mode ? maximum duty cycle distortion 45/55 5.12.3 rgmii clocks the rgmii interface is governed by the hewlett-packard* 1.2a specification. the ixf1104 mac compliant to this spec ification with the following: ? 2.5 v cmos drive ? maximum duty cycle distortion 40/60 ? +/- 100 ppm ? 125 mhz for 1000 mbps, 25 mhz for 100 mbps and 2.5 mhz for 10 mbps 5.12.4 mdc clock the ixf1104 mac support s the ieee 802.3 mii management interface, also known as the management data input/output (mdio) inte rface. the ixf1104 mac meets the following specifications for this clock: ? 2.5 v cmos drive ? 2.5/18 mhz operation (selectable by the mdc speed bit in the mdio control ($0x683) ) ? 50/50 duty cycle for 2.5 mhz operation ? 43/57 duty cycle for 18 mhz operation page 126 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5.12.5 jtag clock the ixf1104 mac supports jtag. the source of this clock must meet the following specifications: ? 2.5 v cmos drive ? maximum clock frequency 11 mhz ? maximum duty cycle distortion 40/60 5.12.6 i 2 c clock the ixf1104 mac supports a single-output i 2 c clock to support al l ten optica l module interfaces. the ixf1104 mac meets the fo llowing specifications for this clock: ? 2.5 v cmos drive ? maximum clock frequency of 100 khz 5.12.7 led clock the ixf1104 mac supports a serial led data stream and meets the following specifications for this clock: ? 2.5 v cmos drive ? maximum frequency of 720 hz ? maximum duty cycle distortion 50/50 page 127 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 6.0 applications 6.1 change port mode initialization sequence use the change port mode initialization sequence after power-up and anytime a port is configured into or switching between fiber or copper mode, switching to/from rgmii and gmii modes, or switching spee ds and duplex in rgmii mode. the following sequence applies to all four ports and can be done simultaneously for all ports or as a subset of the ports. 1. place the mac in reset for the port(s) which require a change by asserting (set to 1) the section 106, mac soft reset ($0x505) . 2. place the tx fifo in reset for the port(s) which require a change by asserting (set to 1) the section 137, tx fifo port reset ($0x620) . 3. disable the port(s) which require change by de-asserting (set to 0) the appropriate bits in the section 103, port enable ($0x500) . 4. wait 1 s. 5. de-assert (set to 0) section 152, clock and interface mode change enable ports 0 - 3 ($0x794) for the ports being changed. 6. set the speed, mode, and duplex as follows for the ports being changed: a. copper mode: select copper mode for the section 104, interface mode ($0x501) ports. set the per-port section 82, mac if mode and rgmii speed ($ port_index + 0x10) to the appropriate speed and rgmii/gmii interface setting. set the per-port section 71, desired duplex ($ port_index + 0x02) . note: half-duplex is supported only when rgmii 10 mbps or 100 mbps is selected in the section 82, mac if mode and rgmii speed ($ port_index + 0x10) . b. fiber mode: select fiber mode by setting the appropriate bit to 0 in the section 104, interface mode ($0x501) ports. 7. assert (set to 1) section 152, clock and interface mode change enable ports 0 - 3 ($0x794) for the ports being changed. 8. wait 1 s. 9. de-assert (set to 0) section 106, mac soft reset ($0x505) for the ports being changed. 10. de-assert (set to 0) section 137, tx fifo port reset ($0x620) for the ports being changed. 11. wait 1 to 2 s. 12. set the section 90, diverse config write ($ port_index + 0x18) to the appropriate value as follows: a. copper mode: write the reserved bits to the default value. page 128 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 enable packet padding and crc appending on transmitted packets in bits 6 and 7, as needed. set bit 5 to 0x0. b. fiber mode: write the reserved bits to the default value. enable packet padding and crc appending on transmitted packets in bits 6 and 7, as needed. set bit 5 to 1 to enable auto-negotiation. set bit 5 to 0 to enable forced mode operation. 13. assert (set to 1) section 103, port enable ($0x500) . 14. wait 1 to 2 s. 15. perform additional device configurations, as needed. 6.2 disable and enab le port sequences cortina recommends the following sequences to disable and enable individual ports, and for dropped links. when a link is dropped, cortina recommends the port be completely reset and flushed to remove packet fragments that may interfere with the auto-negotiation process on link recovery. 6.2.1 disable port sequence use the following sequence to disable an individual port: 1. disable the port using mac port enable/disable bits [ section 103, port enable ($0x500) bits (3-0)]. 2. apply tx fifo soft reset [ section 137, tx fifo port reset ($0x620) bits(3-0)]. 3. introduce some delay to allow completion of packet transmission (not necessary if link is dropped). 4. flush tx [ section 83, flush tx ($ port_index + 0x11) bit 0]. 5. apply mac soft reset [ section 106, mac soft reset ($0x505) bits(3-0)]. 6. apply rx fifo soft reset [ section 122, rx fifo port reset ($0x59e) bits(3:0)]. 6.2.2 enable port sequence use the following sequence to enable an individual port: 1. enable the port(s) using mac port enable/disable bits [ section 103, port enable ($0x500) bits (3-0)]. 2. disable tx fifo soft reset [ section 137, tx fifo port reset ($0x620) bits(3-0)]. 3. reset flush tx [ section 83, flush tx ($ port_index + 0x11) bit 0]. 4. disable mac soft reset [ section 106, mac soft reset ($0x505) bits(3-0)]. 5. disable rx fifo soft reset [ section 122, rx fifo port reset ($0x59e) bits(3:0)]. page 129 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 7.0 electrical specifications table 39 through table 58, led interface ac timing parameters , on page 147 and figure 34, spi3 receive interface timing , on page 133 through figure 51, led ac interface timing , on page 147 represent the target specifications of the following ixf1104 mac interfaces: ? spi3 ?jtag ?mdio ? pause control ?cpu ?led ? system ? gmii and rgmii ?serdes ? optical module these specifications are not guaranteed a nd are subject to change without notice. minimum and maximum values listed in table 41, dc specifications , on page 131 through table 58, led interface ac timing parameters , on page 147 apply over the recommended operating conditions specified in table 40 . table 39 absolute maximum ratings parameter symbol min max units comments supply voltage vdd -0.3 2.2 volts core digital power vdd2, vdd3 -0.3 4.25 volts i/o digital power vdd4, vdd5 -0.3 4.25 volts i/o digital power avdd1p8_1/2 -0.3 2.2 volts analog power avdd2p5_1/2 -0.3 4.25 volts analog power operating temperature ambient topa -40 +85 c copper mode ambient topa 0.0 +70 c fiber mode storage temperature tst -40 +150 c ? caution: exceeding these values may cause permanent damage to the device. functional operation under these cond itions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. page 130 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 7.1 dc specifications the ixf1104 mac supports the following i/o buffer types: ? 2.5 v cmos ? 3.3 v lvttl ?serdes see section 5.1.7, packet buffer dimensions , on page 79 for additional information regarding i/o buffer types. the related driver characteristics are described in this section. table 40 recommended operating conditions parameter symbol min typ max units recommended supply voltage vdd 1.65 ? 1.95 volts vdd2, vdd3 3.0 ? 3.6 volts vdd4, vdd5 2.3 ? 2.7 volts avdd1p8_1 avdd1p8_2 1.65 ? 1.95 volts avdd2p5_1 avdd2p5_2 2.3 ? 2.7 volts operating current serdes operation transmitting and receiving in 1000 mbps mode vdd avdd1p8_1 avdd1p8_2 ? 0.780 ? amps vdd4 vdd5 avdd2p5_1 avdd2p5_2 ? 0.050 ? amps vdd2, vdd3 ? 0.246 ? amps operating current rgmii operation transmitting and receiving in 1000 mbps mode vdd avdd1p8_1 avdd1p8_2 ? 0.757 ? amps vdd4 vdd5 avdd2p5_1 avdd2p5_2 ? 0.224 ? amps vdd2, vdd3 ? 0.208 0.235 amps recommended operating temperature ambient topa 0 ? 70 c case with heat sink topc-hs 0 ? 122 c case without heat sink topc-nhs 0 ? 121 c power consumption serdes operation transmitting and receiving in 1000 mbps mode ? ? 2.23 2.72 watts rgmii operation transmitting and receiving in 1000 mbps mode ? ? 2.84 3.4 watts page 131 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 caution: ixf1104 mac input signals are not 5 v tolera nt. devices driving the ixf1104 mac must provide 3.3 v signal levels or use level-shifting buffers to provide 3.3 v-compatible levels. otherwise, damage to the ixf1104 mac will occur. table 41 dc specifications parameter symbol min typ max units comments 2.5 v cmos i/o cells input high voltage vih 1.7 ? ? v 2.5 v i/os input low voltage vil ? ? 0.7 v 2.5 v i/os output high voltage voh 2.0 ? ? v 2.5 v i/os output low voltage vol ? ? 0.4 v 2.5 v i/os 3.3 v i/o cells input high voltage vih 1.7 ? ? v 3.3 v lvttl i/os input low voltage vil ? ? 0.7 v 3.3 v lvttl i/os output high voltage voh 2.4 ? ? v 3.3 v lvttl i/os output low voltage vol ? ? 0.4 v 3.3 v lvttl i/os table 42 serdes transmit characteristics (sheet 1 of 2) parameter symbol normalize d power drive settings 1 min typ max units comments transmit differential signal level txdfpp 0.50 180 230 325 mvpp diff avdd1p8_2 terminated to 1.8v; rload = 50 1.00 350 440 700 1.33 425 580 900 2.00 600 770 1050 transmit common mode voltage range txcmv 0.50 1300 1600 1940 mv avdd1p8_2 terminated to 1.8v; rload = 50 ohms; fir coeffs = 0 1.00 1000 1400 1870 1.33 800 1300 1825 2.00 700 1100 1760 differential signal rise/ fall time diff rise/ fall 1.00 60 96 132 ps rload = 50 ; 20% to 80% max differential output impedance txdiffz ? 60 105 150 diff nominal value = 100 differential receiver differential voltage requirement at center of receive eye rxdiffv ? 200 ? ? mvp-p diff ? 1. refer to section 5.6.2.2, transmitter programmable driver-power levels , on page 103 . page 132 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 7.1.1 undershoot / overshoot specifications the overshoot figures given in this section represent the maximum voltage that can be applied without affecting the re liability of the device (see table 44 ). caution: if these limits are exceeded, dam age to the device will occur. 7.1.2 rgmii electrical characteristics the rgmii signals (including mdio/mdc) are based on 2.5v cmos interface voltages, as defined by jedec eia/jesd8-5 (see table 45 ). receiver common mode voltage range rxcmv ? 900 1275 1650 mv ? receiver termination impedance rxz ? 40 51 62.5 ? signal detect level rxsigdet ? 50 125 200 mvp- pdiff ? table 42 serdes transmit characteristics (sheet 2 of 2) parameter symbol normalize d power drive settings 1 min typ max units comments 1. refer to section 5.6.2.2, transmitter programmable driver-power levels , on page 103 . table 43 serdes receive characteristics parameter symbol normalize d power drive settings min typ max units comments receiver differential voltage requirement at center of receive eye rxdiffv ? 200 ? ? mvp-p diff ? receiver common mode voltage range rxcmv ? 900 1275 1650 mv ? receiver termination impedance rxz ? 40 51 62.5 ? signal detect level rxsigdet ? 50 125 200 mvp-pdiff ? table 44 undershoot / overshoot limits pin type undershoot overshoot 2.5 v cmos -0.60 v 3.9 v 3.3 v lvttl -0.60 v 3.9 v page 133 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 7.2 spi3 ac timing specifications 7.2.1 receive interface timing figure 34 and table 46 illustrate and provide spi3 receiv e interface timi ng information. table 45 rgmii power symbol parameter conditions min max units v oh output high voltage i oh = -1.0 m a; v dd = m in 2.0 vdd +.3 v v ol output low voltage i ol = 1.0 m a; v dd = m in gnd -.3 0.40 v v ih input high voltage v ih > v ih _m in ; v dd = m in ? vdd +.3 v v il input low voltage v il < v il _m ax ; v dd = m in ?.70v i ih input high current v dd = m ax ; v in = 2.5v ? 15 a i il input low current v dd = m ax ; v in = 0.4v -15 ? a figure 34 spi3 receive interface timing rfclk renb rdat[31:0] rpry rmod rsop reop rerr rval rsx threnb tsrenb tprdat tprprty tprmod tprsop tpreop tprerr tprval tprsx page 134 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 46 spi3 receive in terface signal parameters symbol parameter min max units ? rfclk frequency 90 133 mhz ? rfclk duty cycle 45 55 % tsrenb renb setup time to rfclk 1.8 ? ns threnb renb hold time to rfclk 0.5 ? ns tprdat rfclk high to rdat valid 1.5 3.7 ns tprprty rfclk high to rprty valid 1.5 3.7 ns tprsop rfclk high to rsop valid 1.5 3.7 ns tpreop rfclk high to reop valid 1.5 3.7 ns tprmod rfclk high to rmod valid 1.5 3.7 ns tprerr rfclk high to rerr valid 1.5 3.7 ns tprval rfclk high to rval valid 1.5 3.7 ns tprsx rfclk high to rsx valid 1.5 3.7 ns notes: receive i/o timing 1. when a setup time is specified between an input and a clock, the setup time is the time in nanoseconds from the 1.4-volt point of the input to the 1.4-volt point of the clock. 2. when a hold time is specified between an input and a cloc k, the hold time is the time in nanoseconds from the 1.4-volt point of the clock to the 1.4-volt point of the input. 3. output propagation time is the time in nanoseconds fr om the 1.4-volt point of the reference signal to the 1.4-volt point of the output. 4. maximum propagation delays are measured with a 30 pf load when operating oif-spi3 standard 104 mhz. over-clocked rates of 125 mhz or higher are measured using a load of 20 pf. page 135 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 7.2.2 transmit interface timing figure 35 and table 47 illustrate and provide spi3 transmit interfac e timing in formation. figure 35 spi3 transmit interface timing tfclk tenb tdat[31:0] tprty tmod[1:0] tsop teop terr tadr tsx thtenb tstenb thtdat tstdat thtprty tstrpty thtmod tstmod thtsop tstsop thteop tsteop thterr tsterr thtadr tstadr thtsx tstsx dtpa tpdtpa stpa tpstpa ptpa tpptpa page 136 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 47 spi3 transmit interface signal parameters symbol parameter min max units ? tfclk frequency ? 133 mhz ? tfclk duty cycle 45 55 % tstenb tenb setup time to tfclk 1.8 ? ns thtenb tenb hold time to tfclk 0.5 ? ns tstdat tdat[31:0] setup time to tfclk 1.8 ? ns thtdat tdat[31:0} hold time to tfclk 0.5 ? ns tstprty trpty setup time to tfclk 1.8 ? ns thtprty tprty hold time to tfclk 0.5 ? ns tstsop tsop setup time to tfclk 1.8 ? ns thtsop tsop hold time to tfclk 0.5 ? ns tsteop teop setup time to tfclk 1.8 ? ns thteop teop hold time to tfclk 0.5 ? ns tstmod tmod setup time to tfclk 1.8 ? ns thtmod tmod hold time to tfclk 0.5 ? ns tsterr terr setup time to tfclk 1.8 ? ns thterr terr hold time to tfclk 0.5 ? ns tstsx tsx setup time to tfclk 1.8 ? ns thtsx tsx hold time to tfclk 0.5 ? ns tstadr tadr setup time to tfclk 1.8 ? ns thtadr tadr hold time to tfclk 0.5 ? ns tpdtpa tfclk high to dtpa valid 1.5 3.7 ns tpstpa tfclk high to stpa valid 1.5 3.7 ns tpptpa tfclk high to ptpa valid 1.5 3.7 ns notes: transmit i/o timing: 1. when a setup time is specified between an input and a clock, the setup time is the time in nanoseconds from the 1.4 v point of the input to the 1.4-volt point of the clock. 2. when a hold time is specified betw een an input and clock, the hold time is the time in nanoseconds from the 1.4 v point of the clock to the 1.4-volt point of the input. 3. output propagation delay time is the time in nanosec onds from the 1.4 v point of the reference signal to the 1.4 v point of the output. page 137 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 7.3 rgmii ac timing specification figure 36 and table 48 provide rgmii interface timing parameters. 7.4 gmii ac timing specification 7.4.1 1000 base-t operation figure 37 and figure 38 and table 49 and table 50 provide gmii ac timing specifications. figure 36 rgmii interface timing b3251-01 tskewt txc (at transmitter) txc (at receiver) td[3:0] tx_ctl[n] tskewr td[3:0] td[7:4] txen txerr tskewt rxc (at transmitter) rxc (at receiver) rd[3:0] rx_ctl tskewr rd[3:0] rd[7:4] rxdv rxerr table 48 rgmii interface timing parameters symbol parameter min typ max unit tskewt data-to-clock output skew (at transmitter) -500 0 500 ps tskewr data-to-clock input skew (at receiver) 1 1?2.8ns tcyc clock cycle duration 2 7.2 8 8.8 ns duty_t duty cycle for gigabit 2 45 50 55 % duty_g duty cycle for 10/100t 3 40 50 60 % tr/tf rise/fall time (20?80%) ? ? .75 ns 1. this implies that pc board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. 2. for 10 mbps and 100 mbps tcyc scales to 400 ns +/? 40 ns and 40 ns +/? 4 ns respectively. 3. duty cycle may be stretched/shrunk during speed c hanges or while transitioning to a received packet?s clock domain, as long as minimum dut y cycle is not violated and stretching occurs for no more than three tcyc of the lowest speed transitioned between. page 138 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 7.4.1.1 1000 base-t transmit interface 7.4.1.2 1000base-t receive interface figure 37 1000base-t transmit interface timing b0634-01 gtx_clk txen txd[7:0] txer cps t1 t3 t4 t2 table 49 gmii 1000base-t tr ansmit signal parameters symbol parameter min typ 1 max unit 2 t1 txd[7:0], txen, txer set-up to txc high 2.5 ? ? ns t2 txd[7:0], txen, txer hold from txc high 0.5 ? ? ns t3 txen sampled to crs asserted ? ? 16 bt t4 txen sampled to crs de-asserted ? ? 16 bt 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the phy and is the reciprocal of bit rate. bt for 1000base-t = 10 -9 or 1 ns. figure 38 1000base-t receive interface timing rxdv rxd[7:0] crs t1 t2 rx_clk page 139 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 7.5 serdes ac timing specification 7.6 mdio ac timing specification the mdio interface on the ixf1104 mac can operate in two modes ? low-speed and high-speed. in low-speed mode, the mdc cloc k signal operates at a frequency of 2.5 mhz. in high-speed mode, the mdc clock signal operates at a frequency of 18 mhz. (see figure 40 through figure 43 and table 52 .) table 50 gmii 1000base-t receive signal parameters symbol parameter min typ 1 max unit 2 t1 rxd[7:0], rx_dv, rxer setup to rx_clk high 2.0 ? ? ns t2 rxd[7:0], rx_dv, rxer hold after rx_clk high 0.0 ? ? ns 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the phy and is the reciprocal of bit rate. bt for 1000base-t = 10 -9 or 1 ns. figure 39 serdes timing diagram table 51 serdes timing parameters symbol parameter min max units tt transmit eye width 800 ? ps rt receiver eye width 280 ? ps tv transmit amplitude 1000 ? mv rv receiver amplitude 200 ? mv page 140 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 7.6.1 mdc high-speed operation timing 7.6.2 mdc low-speed operation timing figure 40 mdc high-speed operation timing 24 ns (3 x 125 mhz clocks) 32 ns (4 x 125 mhz clocks) mdc 56 ns (17.85 mhz) figure 41 mdc low-speed operation timing 200 n s (25 x 125 mhz clocks) 200 n s (25 x 125 mhz clocks) mdc 400 ns (2.5 mhz) page 141 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 7.6.3 mdio ac timing figure 42 mdio write timing diagram t1 mdc mdio t2 v max v mi n figure 43 mdio read timing diagram t3 mdc mdio v ma x table 52 mdio timing parameters parameter symbol min typ 1 max units test conditions mdio setup before mdc. t1 10 ? ? ns mdc = 17.8 mhz 10 ? ? ns mdc = 2.5 mhz mdio hold after mdc. t2 10 ? ? ns mdc = 17.8 mhz 10 ? ? ns mdc = 2.5 mhz mdc to mdio output delay t3 0 ? 42 ns mdc = 17.8 mhz 0 ? 300 ns mdc = 2.5 mhz 1. typical values are at 25 o c and are for design aid only; not guaranteed and not subject to production testing. page 142 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 7.7 optical module and i 2 c ac timing specification 7.7.1 i 2 c interface timing figure 44 and figure 45 illustrate bus timing and write cycle, and table 53 shows the i 2 c interface ac timing characteristics. figure 44 bus timing diagram i 2 c_clk i 2 c_data out t dh t sv.sat t aa t buf t hd.sta t high t r t su.sto t su.dat t hd.dat t low t f i 2 c_data in t low figure 45 write cycle diagram ack 8th bit word n i 2 c_clk i 2 c_data stop condition start condition t wr (1) table 53 i 2 c ac timing characte ristics (sheet 1 of 2) symbol parameter min max units f scl clock frequency, scl - 100 khz t low clock pulse width low 4.7 s t high clock pulse width high 4.0 s t i noise suppression 100 s t aa clock low to data valid out 0.1 4.5 s t buf time the bus must be free before a new transmission starts 4.7 - s t hd.sta start hold time 4.0 - s page 143 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 7.8 cpu ac timing specification 7.8.1 cpu interface read cycle ac timing figure 46 , figure 47 , and table 54 illustrate the cpu interfac e read and write cycle ac timing. t su.sta start setup time 4.7 ? s t hd.dat data in hold time 0 ? s t su.dat data in setup time 200 ? ns t r inputs rise time ? 1.0 s t f inputs fall time ? 300 ns t su.sto stop setup time 4.7 ? s t dh data out hold time 100 ? ns t wr write cycle time ? 10 ms table 53 i 2 c ac timing characte ristics (sheet 2 of 2) symbol parameter min max units figure 46 cpu interface read cycle ac timing t cas t cah t crr t cdrs t cdrh t cdrd t crh upx_add[12:0] upx_rdn upx_csn upx_data[31:0] upx_rdyn page 144 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 7.8.2 cpu interface write cycle ac timing 7.9 transmit pause control ac timing specification figure 48 and table 55 show the pause control ac timing specifications. the pause control interface operates as an asynchronous interface relative to the main system clock (clk125). there is, however, a relation ship between the txpauseadd bus and the strobe signal (txpausefr). figure 47 cpu interfac e write cycle ac timing t cas t cah t cwl t cdws t cdwd t cyd t cwh upx_add[12:0] upx_wrn upx_csn upx_data[31:0] upx_rdyn t cdwh table 54 cpu interface write cycle ac signal parameters symbol parameter min max tcas address, chip select setup time 5 ns ? tcah address, chip select hold time 10 ns ? tcrr ready assertion to read de-assertion 10 ns ? tcrh read high width 24 ns ? tcdrs read data setup time to ready assertion 10 ns ? tcdrh read data hold time after read de-assertion 8 ns 32 ns tcdrd read data driving delay 24 ns 355 ns tcwl write assertion width 40 ns ? tcwh ready assertion to write assertion 16 ns ? tcdws write data setup to write de-assertion 10 ns ? tcdwh write data hold time after ready assertion 5 ns ? tcdwd write data sampling delay 8 ns 32 ns tcyd ready width in write cycle 24 ns 40 ns page 145 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 figure 48 pause control interface timing txpauseadd[1:0] txpausefr tsu(min) = 16 ns thold(min) = 16 ns tpw(min) = 16 ns 000 : xon packet on all ports 001 : xoff port0 010 : xoff port1 011 : xoff port2 100 : xoff port3 110-101 : reserved 111 : xoff on all ports txpauseadd[2:0] table 55 transmit pause control interface timing parameters symbol parameter min max units tsu txpauseadd stable prior to txpausefr high 16 ? ns tpw txpausefr pulse width 16 ? ns thold txpauseadd stable after txpausefr high 16 ? ns page 146 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 7.10 jtag ac timing specification figure 49 and table 56 provide the jtag ac timing specifications. 7.11 system ac timi ng specification figure 50 and table 57 illustrate the system reset ac timing specifications. figure 49 jtag ac timing table 56 jtag ac timing parameters symbol parameter min max units tjc tclk cycle time 90 - ns tjh tclk high time 0.4 x tjc 0.6 x tjc ns tjl tclk low time 0.4 x tjc 0.6 x tjc ns tjval tclk falling edge to tdo valid - 25 ns tjsu tms/tdi setup to tclk 20 - ns tjsh tms/tdi hold from tclk 5 - ns figure 50 system reset ac timing page 147 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 7.12 led ac timing specification figure 51 and table 58 provide the led ac timing specifications. table 57 system reset ac timing parameters symbol parameter min max units trw reset pulse width 1.0 - s trt reset recovery time 200 - s figure 51 led ac interface timing led_clk led_data led_latch tcyc tlow thi tdatd thatl tlath table 58 led interface ac timing parameters symbol parameter min max units tcyc led_clk cycle time 1.36 1.40 ms thi led_clk high time 680 700 s tlow led_clk low time 680 700 s tdatd led_clk falling edge to led_data valid 2 5 ns tlath led_clk rising edge to led_latch rising edge 690 700 s tlatl led_clk falling edge to led_latch falling edge 690 700 s page 148 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 8.0 register set the registers shown in this section provide access for configurati on, alarm monitoring, and control of the chip. table 59, mac control registers ($ port index + offset) , on page 149 through table 69, optical module registers ($ 0x799 - 0x79f) , on page 155 provide register map details. the registers ar e listed by ascending address in the table. 8.1 document structure the following sections are structured to prov ide a general overview of the register map. later sections provide detailed descriptions of each register segment or bit. all registers are accessed and addressed as 32-bit doublewords. when accessed using 8- or 16-bit accesses, the cpu interface packs or unpacks the partial accesses into a 32- bit register value. 8.2 graphical representation figure 52 represents an overview of the ixf1104 mac global control status registers that are used to configure or report on all ports. all register locations shown in figure 52 represent a 32-bit double word. figure 52 memory overview diagram b0744-01 global configuration reserved reserved reserved reserved reserved reserved port 3 mac control & statistics port 2 mac control & statistics port 1 mac control & statistics port 0 mac control & statistics - rx block configuration - tx block configuration 0x7ff 0x500 0x480 0x400 0x380 0x300 0x280 0x200 0x180 0x100 0x080 0x000 page 149 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 8.3 per port registers section 8.4 covers all of the registers that are rep licated in each port of the ixf1104 mac. these registers perform an identical function in each port. the address vector for the ixf1104 mac is 11 bits wide. this allows for 7 bits of port- specific access and a 4-bit vector to addre ss each port and all global registers. the address format is shown in figure 53 . 8.4 register map table 59 through table 69, optical module registers ($ 0x799 - 0x79f) , on page 155 present the ixf1104 mac memory map details. global control and status registers are used to configure or report on all ports, and some registers are replicated on a per-port basis. note: all ixf1104 mac registers are 32 bits. figure 53 register overview diagram port select & global registers per-port registers 10 0 6 table 59 mac control registers ($ port index + offs et) (sheet 1 of 2) register bit size mode 1 ref page offset section 70, station address ($ port_index +0x00 ? +0x01) low 32 r/w page 156 0x00 section 70, station address ($ port_index +0x00 ? +0x01) high 32 r/w page 156 0x01 section 71, desired duplex ($ port_index + 0x02) 32 r/w page 156 0x02 section 72, fd fc type ($ port_index + 0x03) 32 r/w page 156 0x03 reserved 32 r ? 0x04 section 73, collision distance ($ port_index + 0x05) 32 r/w page 157 0x05 section 74, collision threshold ($ port_index + 0x06) 32 r/w page 157 0x06 section 75, fc tx timer value ($ port_index + 0x07) 32 r/w page 157 0x07 section 76, fd fc address ($ port_index + 0x08 ? + 0x09) fdfcaddresslow 32 r/w page 157 0x08 section 76, fd fc address ($ port_index + 0x08 ? + 0x09) fdfcaddresshigh 32 r/w page 157 0x09 section 77, ipg receive time 1 ($ port_index + 0x0a) 32 r/w page 158 0x0a section 78, ipg receive time 2 ($ port_index + 0x0b) 32 r/w page 158 0x0b section 79, ipg transmit time ($ port_index + 0x0c) 32 r/w page 158 0x0c reserved ? ro ? 0x0d section 80, pause threshold ($ port_index + 0x0e) 32 r/w page 159 0x0e page 150 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 section 81, max frame size (addr: port_index + 0x0f) 32 r/w page 159 0x0f section 82, mac if mode and rgmii speed ($ port_index + 0x10) 32 r/w page 160 0x10 section 83, flush tx ($ port_index + 0x11) 32 r/w page 160 0x11 section 84, fc enable ($ port_index + 0x12) 32 r/w page 160 0x12 section 85, fc back pressure length ($ port_index + 0x13) 32 r/w page 161 0x13 section 86, short runts threshold ($ port_index + 0x14) 32 r/w page 162 0x14 section 87, discard unknown control frame ($ port_index + 0x15) 32 r/w page 162 0x15 section 88, rx config word ($ port_index + 0x16) 32 ro page 162 0x16 section 89, tx config word ($ port_index + 0x17) 32 r/w page 163 0x17 section 90, diverse config write ($ port_index + 0x18) 32 r/w page 164 0x18 section 91, rx packet filter control ($ port_index + 0x19) 32 r/w page 165 0x19 section 92, port multicast address ($ port_index +0x1a ? +0x1b) portmulticastaddresslow 32 r/w page 166 0x1a section 92, port multicast address ($ port_index +0x1a ? +0x1b) portmulticastaddresshigh 32 r/w page 166 0x1b table 59 mac control registers ($ port index + offs et) (sheet 2 of 2) register bit size mode 1 ref page offset table 60 mac rx statistics registers ($ port index + offset) (sheet 1 of 2) register bit size mode 1 ref page offset rxoctetstotalok 32 r page 167 0x20 rxoctetsbad 32 r page 167 0x21 rxucpckts 32 r page 167 0x22 rxmcpkts 32 r page 167 0x23 rxbcpkts 32 r page 167 0x24 rxpkts64octets 32 r page 167 0x25 rxpkts65to127octets 32 r page 167 0x26 rxpkts128to255octets 32 r page 167 0x27 rxpkts256to511octets 32 r page 167 0x28 rxpkts512to1023octets 32 r page 167 0x29 rxpkts1024to1518octets 32 r page 167 0x2a rxpkts1519tomaxoctets 32 r page 167 0x2b rxfcserrors 32 r page 167 0x2c rxtagged 32 r page 167 0x2d rxdataerror 32 r page 167 0x2e rxalign errors 32 r page 167 0x2f rxlongerrors 32 r page 167 0x30 page 151 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 rxjabbererrors 32 r page 167 0x31 pausemaccontrolreceivedcounter 32 r page 167 0x32 rxunknownmaccontrolframecounter 32 r page 167 0x33 rxverylongerrors 32 r page 167 0x34 rxrunterrors 32 r page 167 0x35 rxshorterrors 32 r page 167 0x36 rxcarrierextenderror 32 r page 167 0x37 rxsequenceerrors 32 r page 167 0x38 rxsymbolerrors 32 r page 167 0x39 table 60 mac rx statistics registers ($ port index + offset) (sheet 2 of 2) register bit size mode 1 ref page offset table 61 mac tx statistics regi sters ($ port index + offset) register bit size mode 1 ref page offset octetstransmittedok 32 r page 171 0x40 octetstransmittedbad 32 r page 171 0x41 txucpkts 32 r page 171 0x42 txmcpkts 32 r page 171 0x43 txbcpkts 32 r page 171 0x44 txpkts64octets 32 r page 171 0x45 txpkts65to127octets 32 r page 171 0x46 txpkts128to255octets 32 r page 171 0x47 txpkts256to511octets 32 r page 171 0x48 txpkts512to1023octets 32 r page 171 0x49 txpkts1024to1518octets 32 r page 171 0x4a txpkts1519tomaxoctets 32 r page 171 0x4b txdeferred 32 r page 171 0x4c txtotalcollisions 32 r page 171 0x4d txsinglecollisions 32 r page 171 0x4e txmultiplecollisions 32 r page 171 0x4f txlatecollisions 32 r page 171 0x50 txexcessivecollisionerrors 32 r page 171 0x51 txexcessivedeferralerrors 32 r page 171 0x52 txexcessivelengthdrop 32 r page 171 0x53 txunderrun 32 r page 171 0x54 txtagged 32 r page 171 0x55 txcrcerror 32 r page 171 0x56 txpauseframes 32 r page 171 0x57 txflowcontrolcollisionssend 32 r page 171 0x58 page 152 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 62 phy autoscan regist ers ($ port index + offset) register bit size mode 1 ref page offset section 95, phy control ($ port index + 0x60) 32 ro page 174 0x60 section 96, phy status ($ port index + 0x61) 32 ro page 175 0x61 section 97, phy identification 1 ($ port index + 0x62) 32 ro page 176 0x62 section 98, phy identification 2 ($ port index + 0x63) 32 ro page 177 0x63 section 99, auto-negotiation advertisement ($ port index + 0x64) 32 ro page 177 0x64 section 100, auto-negotiation link partner base page ability ($ port index + 0x65) 32 ro page 178 0x65 section 101, auto-negotiation expansion ($ port index + 0x66) 32 ro page 179 0x66 section 102, auto-negotiation next page transmit ($ port index + 0x67) 32 ro page 180 0x67 reserved 32 ro ? 0x68 - 0x6f table 63 global status and config uration registers ($ 0x500 - 0x50c) register bit size mode 1 ref page address section 103, port enable ($0x500) 32 r/w page 181 0x500 section 104, interface mode ($0x501) 32 r/w page 181 0x501 section 105, link led enable ($0x502) 32 r/w page 182 0x502 reserved 32 ro ? 0x503 - 0x504 section 106, mac soft reset ($0x505) 32 r/w page 182 0x505 section 107, mdio soft reset ($0x506) 32 r/w page 183 0x506 reserved 32 ro ? 0x507 section 108, cpu interface ($0x508) 32 r/w page 183 0x508 section 109, led control ($0x509) 32 r/w page 183 0x509 section 110, led flash rate ($0x50a) 32 r/w page 184 0x50a section 111, led fault disable ($0x50b) 32 r/w page 184 0x50b section 112, jtag id ($0x50c) 32 r page 185 0x50c table 64 rx fifo registers ($ 0x580 - 0x5bf) (sheet 1 of 2) register bit size mode 1 ref page address section 113, rx fifo high watermark port 0 ($0x580) 32 r/w page 185 0x580 section 114, rx fifo high watermark port 1 ($0x581) 32 r/w page 186 0x581 section 115, rx fifo high watermark port 2 ($0x582) 32 r/w page 186 0x582 section 116, rx fifo high watermark port 3 ($0x583) 32 r/w page 186 0x583 reserved 32 ro ? 0x584 - 0x589 section 117, rx fifo low watermark port 0 ($0x58a) 32 r/w page 187 0x58a page 153 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 section 118, rx fifo low watermark port 1 ($0x58b) 32 r/w page 187 0x58b section 119, rx fifo low watermark port 2 ($0x58c) 32 r/w page 187 0x58c section 120, rx fifo low watermark port 3 ($0x58d) 32 r/w page 188 0x58d reserved 32 ro ? 0x58e - 0x593 rx fifo overflow frame drop counter port 0 32 r page 188 0x594 rx fifo overflow frame drop counter port 1 32 r page 188 0x595 rx fifo overflow frame drop counter port 2 32 r page 188 0x596 rx fifo overflow frame drop counter port 3 32 r page 188 0x597 reserved 32 ro ? 0x598 - 0x59d section 122, rx fifo port reset ($0x59e) 32 r/w page 188 0x59e section 123, rx fifo errored frame drop enable ($0x59f) 32 r/w page 189 0x59f section 124, rx fifo overflow event ($0x5a0) 32 r page 190 0x5a0 reserved 32 r ? 0x5a1 - 0x5a5 rx fifo errored frame drop counter port 0 32 r page 191 0x5a2 rx fifo errored frame drop counter port 1 32 r page 191 0x5a3 rx fifo errored frame drop counter port 2 32 r page 191 0x5a4 rx fifo errored frame drop counter port 3 32 r page 191 0x5a5 reserved 32 ro ? 0x5a6 - 0x5b1 section 126, rx fifo spi3 loopback enable for ports 0 - 3 ($0x5b2) 32 r/w page 192 0x5b2 section 127, rx fifo padding and crc strip enable ($0x5b3) 32 r/w page 192 0x5b3 reserved 32 r ? 0x5b4 - 0x5b7 section 128, rx fifo transfer threshold port 0 ($0x5b8) 32 r/w page 193 0x5b8 section 129, rx fifo transfer threshold port 1 ($0x5b9) 32 r/w page 193 0x5b9 section 130, rx fifo transfer threshold port 2 ($0x5ba) 32 r/w page 193 0x5ba section 131, rx fifo transfer threshold port 3 ($0x5bb) 32 r/w page 194 0x5bb reserved 32 r ? 0x5bc - 0x5bf table 64 rx fifo registers ($ 0x580 - 0x5bf) (sheet 2 of 2) register bit size mode 1 ref page address table 65 tx fifo registers ($ 0x600 - 0x63e) (sheet 1 of 2) register bit size mode 1 ref page address tx fifo high watermark port 0 32 r/w page 195 0x600 tx fifo high watermark port 1 32 r/w page 195 0x601 tx fifo high watermark port 2 32 r/w page 195 0x602 tx fifo high watermark port 3 32 r/w page 195 0x603 page 154 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 reserved 32 ro ? 0x604 - 0x609 tx fifo low watermark port 0 32 r/w page 196 0x60a tx fifo low watermark port 1 32 r/w page 196 0x60b tx fifo low watermark port 2 32 r/w page 196 0x60c tx fifo low watermark port 3 32 r/w page 196 0x60d reserved 32 ro ? 0x60e - 0x613 tx fifo mac threshold port 0 32 r/w page 197 0x614 tx fifo mac threshold port 1 32 r/w page 197 0x615 tx fifo mac threshold port 2 32 r/w page 197 0x616 tx fifo mac threshold port 3 32 r/w page 197 0x617 reserved ? ro ? 0x618 - 0x61d tx fifo overflow/underflow event/out of sequence 32 r page 198 0x61e loop rx data to tx fifo 32 r/w page 199 0x61f tx fifo port reset 32 r/w page 199 0x620 tx fifo overflow frame drop counter port 0 32 r page 200 0x621 tx fifo overflow frame drop counter port 1 32 r page 200 0x622 tx fifo overflow frame drop counter port 2 32 r page 200 0x623 tx fifo overflow frame drop counter port 3 32 r page 200 0x624 tx fifo errored frame drop counter port 0 32 r page 201 0x625 tx fifo errored frame drop counter port 1 32 r page 201 0x626 tx fifo errored frame drop counter port 2 32 r page 201 0x627 tx fifo errored frame drop counter port 3 32 r page 201 0x628 reserved 32 r ? 0x629 - 0x62c tx fifo occupancy counter for port 0 32 r page 202 0x62d tx fifo occupancy counter for port 1 32 r page 202 0x62e tx fifo occupancy counter for port 2 32 r page 202 0x62f tx fifo occupancy counter for port 3 32 r page 202 0x630 reserved 32 r ? 0x631 - 0x63e table 65 tx fifo registers ($ 0x600 - 0x63e) (sheet 2 of 2) register bit size mode 1 ref page address table 66 mdio registers ($ 0x680 - 0x683) register bit size mode 1 ref page address section 142, mdio single command ($0x680) 32 r/w page 202 0x680 section 143, mdio single read and write data ($0x681) 32 r/w page 203 0x681 section 144, autoscan phy address enable ($0x682) 32 r/w page 203 0x682 section 145, mdio control ($0x683) 32 r/w page 204 0x683 page 155 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 8.4.1 mac control registers table 70 through table 92, port multicast address ($ port_index +0x1a ? +0x1b) , on page 166 provide details on the control and st atus registers associated with each mac port. the register address is ?port_index + 0x**?, where the port index is set at any value from 0x0 through 0x5. all registers are 32-bi t. the unused bits of the registers are read- only and are set permanently to zero. table 67 spi3 registers ($ 0x700 - 0x716) register bit size mode 1 ref page address section 146, spi3 transmit and global configuration ($0x700) 32 r/w page 204 0x700 section 147, spi3 receive configuration ($0x701) 32 r/w page 207 0x701 reserved 32 r ? 0x702 - 0x709 section 148, address parity error packet drop counter ($0x70a) 32 r page 210 0x70a reserved 32 r ? 0x70b - 0x716 table 68 serdes registers ($ 0x780 - 0x798) register bit size mode 1 ref page address reserved 32 ro ? 0x780 - 0x783 section 149, tx driver power level ports 0 - 3 ($0x784) 32 r/w page 210 0x784 reserved 32 ro ? 0x785 - 0x786 tx and rx power-down ($0x787) 32 r/w page 210 0x787 reserved 32 ro ? 0x788 - 0x792 section 151, rx signal detect level ports 0 - 3 ($0x793) 32 r/w page 211 0x793 section 152, clock and interface mode change enable ports 0 - 3 ($0x794) 32 r/w page 211 0x794 reserved 32 ro ? 0x795 - 0x798 table 69 optical module registers ($ 0x799 - 0x79f) register bit size mode 1 ref page address section 153, optical module status ports 0-3 ($0x799) 32 r page 212 0x799 section 154, optical module control ports 0 - 3 ($0x79a) 32 r/w page 213 0x79a section 155, i 2 c control ports 0 - 3 ($0x79b) 32 r/w page 214 0x79b reserved 32 ro ? 0x79c - 0x79e section 156, i 2 c data ports 0 - 3 ($0x79f) 32 r/w page 214 0x79f page 156 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 70 station address ($ port_index +0x00 ? +0x01) name description address type 1 default station address low source mac address bit 31-0. this address is inserted in the source address field when transmitting pause frames, and is also used to compare against unicast pause frames at the receiving side. port_index + 0x00 r/w 0x0000000 station address high source mac address bit 47-32. this address is inserted in the source address field when transmitting pause frames, and is also used to compare against unicast pause frames at the receiving side. bits 15:0 of this register are assigned to bits 47:32 of the station address. port_index + 0x01 r/w 0x00000000 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 71 desired duplex ($ port_index + 0x02) bit name description type 1 default register description: chooses between half-duplex and full-duplex operation in rgmii 100 mbps or 10 mbps mode only. this register must be set to the default value of 1 and must not be changed when operating in rgmii 1000 mbps, gmii, or fiber mode. 0x00000001 31:1 reserved reserved r 0x00000000 0duplex select 0 = half-duplex 1 = full-duplex note: half-duplex operation applies only to 10/100 mbps speed on copper media in rgmii mode only. gigabit speed on either media requires full-duplex. r/w 1 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 72 fd fc type ($ port_index + 0x03) name description address type 1 default fd fc type this value fills the type field of the transmitted pause frames. only bits 15:0 of this register are used. port_index + 0x03 r/w 0x00008808 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 157 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 73 collision distance ($ port_index + 0x05) name description address type 1 default collision distance this is a 10-bit value that sets the limit for late collision. collisions happening at byte times beyond the configured value are considered to be late collisions. (only valid in half-duplex). port_index + 0x05 r/w 0x00000043 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 74 collision threshol d ($ port_index + 0x06) name description address type 1 default collision threshold this is a 4-bit value that sets the limit for excessive collisions. when the number of transmission attempts performed for a packet exceeds this value, it is considered to be an excessive collision and the frame is dropped. (only valid in half-duplex). port_index + 0x06 r/w 0x0000000f 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 75 fc tx timer value ($ port_index + 0x07) name description address type 1 default fc tx timer value the 16-bit pause length inserted in the flow control pause frame sent to the receiving station. the value is in 512-bit times. port_index + 0x07 r/w 0x0000005e 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 76 fd fc address ($ port_index + 0x08 ? + 0x09) name description address type 1 default fd fc address low the lowest 32 bits of the 48-bit globally assigned multicast pause frame destination address. port_index + 0x08 r/w 0xc2000001 fd fc address high the highest 16 bits (47:32) of the globally assigned multicast pause frame destination address. the higher 16-bit address is derived from bits 15:0 of this register. port_index + 0x09 r/w 0x00000180 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 158 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 77 ipg receive time 1 ($ port_index + 0x0a) name description address type 1 default ipg receive time 1 this timer is used during half-duplex operation when there is a packet waiting for transmission from the mac. this timer starts after crs is de-asserted. if crs is asserted during this time, no transmission is initiated and the counter restarts once crs is de- asserted again. the value specified in this register is calculated as follows: (register_value * 8) = rxipg1 in terms of bit times. therefore, a default value of 8 gives the following: (8 * 8 = 64 bit times for the default). port_index + 0x0a r/w 0x00000008 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 78 ipg receive time 2 ($ port_index + 0x0b) name description address type 1 default ipg receive time 2 this is only used in half-duplex operation. it starts counting at the same time as rxipg1. once rxipg1 expires, a frame is transmitted when rxipg2 expires regardless of the crs value. if crs is asserted before rxipg1 expires, no transmission occurs and both rxipg1 an rxipg2 are reset once crs is de-asserted again. the value specified in this register is calculated as follows: (register_value +5) * 8 = rxipg2 in terms of bit times. therefore, a default of 7 gives the following: (7+5) * 8 = 96 bit times for default. port_index + 0x0b r/w 0x00000007 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 79 ipg transmit time ($ port_index + 0x0c) name description address type 1 default ipg transmit time this is a 10-bit value configuring ipg time for back-to-back transmissions. the value specified in this register is calculated as follows: (register_value +4) * 8 = txipg in terms of bit times. therefore, a default value of 8 gives the following: (8+4) * 8 = 96 bit times for the default. port_index + 0x0c r/w 0x00000008 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 159 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 80 pause threshold ($ port_index + 0x0e) name description address type 1 default pause threshold when a pause frame has been sent, an internal timer checks when the next pause frame must be scheduled for transmission to keep the link partner in pause mode (this is required only if the flow control has to be extended for one more session). the pause threshold value is a 16-bit value that sets the time in terms of 512-bit quantum after the previous pause frame when the next pause frame has to be sent. this ensures that the link partner is kept in pause mode continuously. port_index + 0x0e r/w 0x0000002f 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 81 max frame size (addr: port_index + 0x0f) name description address type 1 default max frame size this is a 14-bit value configuring the maximum frame size the mac can receive or transmit without activating any error counters, and without truncation. this value is excluding the 4-byte crc in the transmit direction when crc append is enabled in the mac. hence, this value has to be set four bytes less when crc append is enabled in the mac. the maximum frame size is internally adjusted by +4 if the frame is vlan tagged. port_inde x + 0x0f r/w 0x000005ee 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 160 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 82 mac if mode and rgmii speed ($ port_index + 0x10) bit name description type 1 default register description ? mac if mode: determines the mac operation frequency and mode per port. changes to the data setting of this regist er must be made in conjunction with the clock and interface mode change enable ports 0 - 3 ($0x794) to ensure a safe transition to a new operational mode. changes to this register must follow a proper sequence. refer to section 6.1, change port mode initialization sequence , on page 127 for the proper sequence for changing the port mode and speed. 0x00000003 31:3 reserved reserved r 0x00000000 2:0 port mode these bits are used to define the clock mode and the rgmii/gmii mode of operation. 000 =reserved 001 =reserved 010 =gmii 1000 mbps operation 011 = reserved 100 =rgmii 10 mbps operation 101 =rgmii 100 mbps operation 11x = rgmii 1000 mbps operation r/w 011 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 83 flush tx ($ port_index + 0x11) bit name description type 1 default register description: used to flush all tx data. it is used if all traffic sent to a port should be stopped. 0x00000000 31:1 reserved reserved r 0x00000000 0flush tx this bit flushes all tx dat a and is used if all the traffic sent to a port should be stopped. r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 84 fc enable ($ port_index + 0x12) (sheet 1 of 2) bit name description type 1 default register description: indicates which flow control mode is used for the rx and tx mac. 0x00000007 31:3 reserved reserved r 0x00000000 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 161 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 2 tx hdfc when tx hdfc is enabled (half-duplex mode only), the mac generates de liberate collisions on incoming packets when the rx fifo occupancy crosses the high watermark (flow control). 0 = disable tx half-duplex flow control 1 = enable tx half-duplex flow control r/w 1 1tx fdfc 0 = disable tx full-duplex flow control [the mac will not generate internally any flow control frames based on the rx fifo watermarks or the transmit pause control interface 1 = enable tx full-duplex flow control [enables the mac to send flow control frames to the link partner based on the rx fifo programmable watermarks or the transmit pause control interface] r/w 1 0rx fdfc 0 = disable rx full-duplex flow control [the mac will not respond to flow c ontrol frames sent to it by the link partner] 1 = enable rx full-duplex flow control [mac will respond to flow control frames sent by the link partner and will stop packet transmission for the time specified in the flow control frame] r/w 1 table 84 fc enable ($ port_index + 0x12) (sheet 2 of 2) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 85 fc back pressure length ($ port_index + 0x13) name description address type 1 default fc back pressure length this register sets number the byte cycles for which the collision has to be applied. the 6-bit configuration holds the value in bytes, which applies to the minimum length/duration of back pressure in half- duplex mode. flow control in the receive path is executed by deliberately colliding the incoming packets in half-duplex mode. register bits 5:0 are used alone. port add + 0x13 r/w 0x0000000c 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 162 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 86 short runts thresh old ($ port_index + 0x14) name description address type 1 default short runts threshold the 5-bit configuration holds the value in bytes, which applies to the threshold in determining between runts and short. the bits 4:0 of this register are alone used. a received packet is reported as a short packet when the length (excluding preamble and sfd) is less than this value. a received packet is reported as a runt packet when the length (excluding preamble and sfd) is equal to or greater than this value and less than 64-bytes. note: this register is only relevant when the ixf1104 mac port is configured for copper operation (the line side interface is configured for either rgmii or gmii). port_index + 0x14 r/w 0x00000008 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 87 discard unknown control frame ($ port_index + 0x15) bit name description type 1 default register description: discards or forwards unknown cont rol frames. known control frames are pause frames. 0x00000000 31:1 reserved reserved r 0x00000000 0 discard unknown control frame 0 = forward unknown control frames 1 = discard unknown control frames r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 88 rx config word ($ port_index + 0x16) (sheet 1 of 2) bit name description type 1 default register description: this register is used in fiber mac only for auto-negotiation and to report the receive status. the lower 16 bits of this regi ster are the ?config_reg? received from the link partner, as described in ieee 802.3 2000 edition, section 37.2.1. 0x00000000 31:22 reserved reserved ro 0x000 21 an_complete auto-negotiation complete. this bit remains cleared from the time auto-negotiation is reset until auto-negotiation reaches the ?link_ok? state. it remains set until auto-negotiation is disabled or restarted. this bit is only valid if auto-negotiation is enabled. ro 0 20 rx sync 0 = loss of synchronization 1 = bit synchronization. the bit remains low until the register is read. ro 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 163 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 19 rx config 0 = receiving idle/data stream 1 = receiving /c/ ordered sets ro 0 18 config changed 0 = rxconfigword has changed since last read 1 = rxconfigword has not changed since last read. this bit remains high until the register is read. r0 17 invalid word 0 = have not received an invalid symbol 1 = have received an invalid symbol this bit remains high until the register is read. ro 0 16 carrier sense 0 = device is not receiving idle characters; carrier sense is true. 1 = device is receiving id le characters; carrier sense is false. ro 0 15 next page next page request ro 0 14 reserved reserved ro 0 13:12 2 remote fault [1:0] remote fault definitions: 00 = no error, link okay 01 = offline 10 = link failure 11 = auto-negotiation_error r/w 00 11:9 reserved reserved ro 000 8 asym pause asym pause. the abi lity to send pause frames. ro 0 7sym pause sym pause. the ability to send and receive pause frames. ro 0 6 half duplex half-duplex ro 0 5 full duplex full-duplex ro 0 4:0 reserved reserved ro 0x0 table 88 rx config word ($ port_index + 0x16) (sheet 2 of 2) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 89 tx config word ($ port_index + 0x17) (sheet 1 of 2) bit name description type 1 default register description: this register is used in fiber mac for auto-negotiation only. the contents of this register are sent as the conf ig_word. the contents of this register are the ?config_reg? sent to the link partner, as descri bed in ieee 802.3 2000 edition, subclause 37.2.1. 0x000001a0 31:16 reserved reserved ro 0x0000 15 next page next page request r/w 0 14 reserved write as 0, ignore on read r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write note: a value of 0x0 must be written to all reserved bits of the section 89, tx config word ($ port_index + 0x17) register. page 164 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 13:12 2 remote fault [1:0] remote fault definitions: 00 = no error, link okay 01 = offline 10 = link failure 11 = auto-negotiation_error r/w 00 11:9 reserved write as 0, ignore on read r/w 000 8 asym pause asym pause. the abili ty to send pause frames. r/w 1 7 sym pause sym pause. the ability to send and receive pause frames. r/w 1 6 half duplex half-duplex r/w 0 5 full duplex full-duplex r/w 1 4:0 reserved write as 0, ignore on read r/w 0x00 table 89 tx config word ($ port_index + 0x17) (sheet 2 of 2) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write note: a value of 0x0 must be written to all reserved bits of the section 89, tx config word ($ port_index + 0x17) register. table 90 diverse config write ($ port_index + 0x18) (sheet 1 of 2) bit name description type 1 default register description: this register contains various configuration bi ts for general use. 0x00110d 31:19 reserved reserved ro 0x0000 18:13 reserved write as 0, ignore on read. r/w 0x0000 12 reserved 2 write as 1, ignore on read. r/w 1 11-9 reserved 2 write as 0, ignore on read. r/w 0x0 8reserved 2 write as 1, ignore on read. r/w 1 7 pad_enable 0 = normal operation 1 = enable padding of undersized packets note: assertion of this bit results in the automatic addition of a crc to the padded packet. r/w 0 6 crc_add 0 = normal operation 1 = enable automatic crc appending r/w 0 5 an_enable enable auto-negotiation (used for fiber mode only) to be performed by the hardware state machines in the mac. the hardware auto-negotiation (an) state machine controls the config words transmitted when this bit is set. note: in copper mode, this bit must be set to 0 (reserved). r/w 0 4 2 reserved write as 0, ignore on read. r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write 2. reserved bits must be written to the default value for proper operation. page 165 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 3:2 2 reserved write as 1, ignore on read. r/w 11 1 2 reserved write as 0, ignore on read. r/w 0 0 2 reserved write as 1, ignore on read. r/w 1 table 90 diverse config write ($ port_index + 0x18) (sheet 2 of 2) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write 2. reserved bits must be written to the default value for proper operation. table 91 rx packet filter control ($ port_index + 0x19) (sheet 1 of 2) bit name description type 1 default register description: this register allows for specific packet types to be marked for filtering and is used in conjunction with the section 125, rx fifo errored frame drop counter ports 0 - 3 ($0x5a2 - 0x5a5) . 0x00000000 31:6 reserved reserved 0 5 crc error pass this bit enables a global fi lter on frames with a crc error. 0 = when crc error pass = 0, all frames with a crc error are marked as bad. 2 1 = frames with a crc error are not marked as bad and are passed to the spi3 interface for transfer as good frames, regardless of the state of the bits in the section 123, rx fifo errored frame drop enable ($0x59f) . note: when the crc error pass filter bit = 0, it takes precedence over the other filter bits. any packet, whether is a pause, unicast, multicast or broadcast packet with a crc error, is marked as a bad frame when crc error pass = 0 r/w 0 4 pause frame pass this bit enables a global filter on pause frames. 0 = all pause frames are dropped. 2 1 = all pause frames are passed to the spi3 interface. note: pause frames can only be filtered if rxfd flow control is enabled in the section 84, fc enable ($ port_index + 0x12) . r/w 0 3 vlan drop en this bit enables a global filter on vlan frames. 0 = all vlan frames are passed to the spi3 interface. 1 = all vlan frames are dropped. 2 r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write 2. used in conjunction with the section table 123, rx fifo errored frame drop enable ($0x59f) , on page 189 . this allows the frame to be dropped in the rx fifo. otherwise, the frame is sent out the sp3 interface and may be optionally si gnaled with an rerr (see bit 0 of section 147, spi3 receive configuration ($0x701) . page 166 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 8.4.2 mac rx statistics register overview the mac rx statistics registers contain the mac receiver statistic counters and are cleared when read. the software polls these registers and accumulates values to ensure that the counters do not wrap. the 32-bit counters wrap after approximately 30 seconds. table 93 covers the rx statistics for the four mac ports. port_index is the port number (0, 1, 2, or 3). 2 b/cast drop en this bit enables a global filter on broadcast frames. 0 = all broadcast frames are passed to the spi3 interface. 1 = all broadcast frames are dropped. 2 r/w 0 1 m/cast match en this bit enables a filter on multicast frames. 0 = all muticast frames are good and passed to the spi3 interface. 1 = only multicast frames with a destination address that matches the portmulticastaddress are forwarded. all other muticast frames are dropped. 2 r/w 0 0 u/cast match en 2 this bit enables a filter on unicast frames. 0 = all unicast frames are good and are passed to the spi3 interface. 1 = only unicast frames with a destination address that matches the station address are forwarded. all other unicast frames are dropped. 2 note: the vlan filter overrides the unicast filter. therefore, a vlan frame cannot be filtered based on the unicast address. r/w 0 table 91 rx packet filter control ($ port_index + 0x19) (sheet 2 of 2) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write 2. used in conjunction with the section table 123, rx fifo errored frame drop enable ($0x59f) , on page 189 . this allows the frame to be dropped in the rx fifo. otherwise, the frame is sent out the sp3 interface and may be optionally si gnaled with an rerr (see bit 0 of section 147, spi3 receive configuration ($0x701) . table 92 port multicast address ($ port_index +0x1a ? +0x1b) name description address type * default port multicast address low this address compares against multicast frames at the receiving side if multicast filtering is enabled. this register contains bits 31:0 of the address. port_index + 0x1a r/w 0x0000000 port multicast address high this address compares against multicast frames at the receiving side if multicast filtering is enabled. this register contains bits 47:32 of the address. port_index + 0x1b r/w 0x00000000 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 167 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 93 mac rx statistics ($ port _index + 0x20 ? + 0x39) (sheet 1 of 4) name description address type 1 default rxoctetstotalok counts the bytes received in all legal frames, including all bytes from the destination mac address to and includi ng the cyclic redundancy check (crc). the initial preamble and start of frame delimiter (sfd) bytes are not counted. port_index + 0x20 r 0x00000000 rxoctetsbad 2 counts the bytes received in all bad frames with legal size (frames with crc error, alignment errors, or code violati ons), including all bytes from the destination mac address to (and including) the crc. the initial preamble and sfd bytes are not counted. frames with illegal size do not add to this counter (shorts, runts, longs, jabbers, and very longs). note: this register does not count octets on undersized received packets. port_index + 0x21 r 0x00000000 rxucpkts the total number of unicast packets received (excluding bad packets). note: this count includes non-pause control and vlan packets, which are also counted in other counters. these packet types are counted twice. take care when summing register counts for reporting management information base (mib) information. port_index + 0x22 r 0x00000000 rxmcpkts the total number of multicast packets received (excluding bad packets) note: this count includes pause control packets, which are also counted in the pausemaccontrol-receivedcounter. these packet types are counted twice. take care when summing register counts for reporting mib information. port_index + 0x23 r 0x00000000 rxbcpkts the total number of broadcast packets received (excluding bad packets). port_index + 0x24 r 0x00000000 rxpkts64octets the total number of packets received (including bad packets) that were 64 octets in length. incremented for tagged packets with a length of 64 bytes, including tag field. port_index + 0x25 r 0x00000000 rxpkts65to127 octets the total number of packets received (including bad packets) that were 65-127 octets in length. incremented for tagged packets with a length of 65-127 bytes, including tag field. port_index + 0x26 r 0x00000000 rxpkts128t0255 octets the total number of packets received (including bad packets) that were 128-255 octets in length. incremented for tagged packets with a length of 128-255 bytes, including tag field. port_index + 0x27 r 0x00000000 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write 2. when sending in large frames, the counters can onl y handle certain limits. the behavior of the longerrors and verylongerrors counters is as follows: very longerrors counts frames that are 2*maxframesize, dependent upon where maxframesize is set. if maxframesize sets greater than half of the available count in rxoctetsbad (2^14-1), verylongerrors is never increm ented, but longerrors is incremented. this is due to a limitation in the counter size, which means that an accurate count will not occur in the rxoctetsbad counter if the frame is larger than 2^14-1. 3. this register is relevant only when configured for copper operation. 4. this register is relevant only when configured for fiber operation (line side interface is serdes). page 168 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 rxpkts256to511 octets the total number of packets received (including bad packets) that were 256-511 octets in length. incremented for tagged packets with a length of 256-511 bytes, including tag field. port_index + 0x28 r 0x00000000 rxpkts512to1023o ctets the total number of packets received (including bad packets) that were 512-1023 octets in length. incremented for tagged packets with a length of 512-1023 bytes, including tag field. port_index + 0x29 r 0x00000000 rxpkts1024to1518 octets the total number of packets received (including bad packets) that were 1024-1518 octets in length. incremented for tagged packet with a length between 1024-1522, including the tag. port_index + 0x2a r 0x00000000 rxpkts1519tomaxo ctets the total number of packets received (including bad packets) that were greater than 1518 octets in length. incremented for tagged packet with a length between 1523-max frame size, including the tag. port_index + 0x2b r 0x00000000 rxfcserrors number of frames received with legal size, but with wrong crc field (also called frame check sequence (fcs) field). note: legal size is 64 bytes through the value programmed in the section table 81, max frame size (addr: port_index + 0x0f) , on page 159 . port_index + 0x2c r 0x00000000 rxtagged number of ok frames with vlan tag. (type field = 0x8100) port_index + 0x2d r 0x00000000 rxdataerror 3 number of frames received with legal length, containing a code violation (signaled with rx_err on rgmii). port_index + 0x2e r 0x00000000 rxalignerrors 3 frames with a legal frame size, but containing less than eight additional bits. this occurs when the frame is not byte aligned. the crc of the frame is wrong when the additional bits are stripped. if the crc is ok, then the frame is not counted but treated as an ok frame. this counter increments in 10 mbps or 100 mbps rgmii mode only. note: this counter increments in 10 or 100 mbps rgmii mode only. port_index + 0x2f r 0x00000000 table 93 mac rx statistics ($ port _index + 0x20 ? + 0x39) (sheet 2 of 4) name description address type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write 2. when sending in large frames, the counters can onl y handle certain limits. the behavior of the longerrors and verylongerrors counters is as follows: very longerrors counts frames that are 2*maxframesize, dependent upon where maxframesize is set. if maxframesize sets greater than half of the available count in rxoctetsbad (2^14-1), verylongerrors is never increm ented, but longerrors is incremented. this is due to a limitation in the counter size, which means that an accurate count will not occur in the rxoctetsbad counter if the frame is larger than 2^14-1. 3. this register is relevant only when configured for copper operation. 4. this register is relevant only when configured for fiber operation (line side interface is serdes). page 169 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 rxlongerrors 2 frames bigger than the maximum allowed, with both ok crc and the integral number of octets. default maximum allowed is 1518 bytes untagged and 1522 bytes tagged, but the value can be changed by a register. frames bigger than the larger of 2*maxframesize and 50,000 bits are not counted here, but they are counted in the verylongerror counter. port_index + 0x30 r 0x00000000 rxjabbererrors frames bigger than the maximum allowed, with either a bad crc or a non-integral number of octets. the default maximum allowed is 1518 bytes untagged and 1522 bytes tagged, but the value can be changed by a register. frames bigger than the larger of 2*maxframesize and 50,000 bits are not counted here, but they are counted in the verylongerror counter. port_index + 0x31 r 0x00000000 rxpausemaccontr olreceivedcounter number of pause mac control frames received. this statistic register increments on any valid 64- byte pause frame with a valid crc and also increments on a 64-byte pause frame with an invalid crc if bit 5 of the section 91, rx packet filter control ($ port_index + 0x19) is set to 1. port_index + 0x32 r 0x00000000 rxunknownmac controlframe counter number of mac control frames received with an op code different from 0001 (pause). port_index + 0x33 r 0x00000000 rxverylongerrors 2 frames bigger than the larger of 2*maxframesize and 50,000 bits port_index + 0x34 r 0x00000000 table 93 mac rx statistics ($ port _index + 0x20 ? + 0x39) (sheet 3 of 4) name description address type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write 2. when sending in large frames, the counters can onl y handle certain limits. the behavior of the longerrors and verylongerrors counters is as follows: very longerrors counts frames that are 2*maxframesize, dependent upon where maxframesize is set. if maxframesize sets greater than half of the available count in rxoctetsbad (2^14-1), verylongerrors is never increm ented, but longerrors is incremented. this is due to a limitation in the counter size, which means that an accurate count will not occur in the rxoctetsbad counter if the frame is larger than 2^14-1. 3. this register is relevant only when configured for copper operation. 4. this register is relevant only when configured for fiber operation (line side interface is serdes). page 170 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 rxrunterrors 3 the total number of packets received that are less than 64 octets in length, but longer than or equal to 96 bit times, which corresponds to a 4- byte frame with a well-formed preamble and sfd. this is the shortest fragment and can be transmitted in case of a collision event on a half- duplex segment. this count er indicates fragment sizes, which is expected on half-duplex segments but not on full-duplex links, and the counter is only fully updated after receipt of a good frame following a fragment. note: the shortruntsthreshold register controls the byte count used to determine the difference between runts and shorts and therefore controls which counter is incremented for a given frame size. this counter is only updated after receipt of two good frames. note: this counter is only valid when the selected port within the ixf1104 mac is operating in copper (rgmii or gmii) mode. the runterror counter is not updated when the selected port within the ixf1104 mac is configured to operated in fiber (serdes) mode. port_index + 0x35 r 0x00000000 rxshort errors 3 the total number of packets received that are less than 96 bit times, which corresponds to a 4- byte frame with a well-formed preamble and sfd. this counter indicates fragment sizes illegal in all modes and is only fully updated after reception of a good frame following a fragment. note: this register is only relevant when the ixf1104 mac port is configured for copper operation (the line side interface is configured for either rgmii or gmii operation). this register will not increment when the ixf1104 mac port is configured for fi ber operation using the serdes interface. port_index + 0x36 r 0x00000000 rxcarrier extend error not applicable. port_index + 0x37 r 0x00000000 rxsequenceerrors 4 records the number of sequencing errors that occur in fiber mode. port_index + 0x38 r 0x00000000 rxsymbolerrors 4 records the number of symbol errors encountered by the phy. port_index + 0x39 r 0x00000000 table 93 mac rx statistics ($ port _index + 0x20 ? + 0x39) (sheet 4 of 4) name description address type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write 2. when sending in large frames, the counters can onl y handle certain limits. the behavior of the longerrors and verylongerrors counters is as follows: very longerrors counts frames that are 2*maxframesize, dependent upon where maxframesize is set. if maxframesize sets greater than half of the available count in rxoctetsbad (2^14-1), verylongerrors is never increm ented, but longerrors is incremented. this is due to a limitation in the counter size, which means that an accurate count will not occur in the rxoctetsbad counter if the frame is larger than 2^14-1. 3. this register is relevant only when configured for copper operation. 4. this register is relevant only when configured for fiber operation (line side interface is serdes). page 171 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 8.4.3 mac tx statistics register overview the mac tx statistics registers contain all the mac transmit statistic counters and are cleared when read. the software must poll t hese registers to accumulate values and to ensure that the counters do not wrap. th e 32-bit counters wrap after approximately 30 seconds. table 94 covers all four mac ports tx statistics. port_index is the port number (0, 1, 2, or 3). table 94 mac tx statistics ($ port_index +0x40 ? +0x58) (sheet 1 of 4) name description address type 1 default octetstransmittedok counts the bytes transmitted in all legal frames. the count includes all bytes from the destination mac address to and including the crc. the initial preamble and sfd bytes are not counted. any initial collided transmission attempts before a successful frame transmission do not add to this counter. port_index + 0x40 r 0x00000000 octetstransmittedbad counts the bytes transmitted in all bad frames. the count includes all bytes from the destination mac address to and including the crc. the initial preamble and sfd bytes are not counted. late collision counted: the count is close to the actual number of bytes transmitted before the frame is discarded. excessive collision counted: the count is close to the actual number of bytes transmitted before the frame is discarded. tx under-run counted: the count is expected to match the number of bytes actually transmitted before the frame is discarded. tx crc error counted: all bytes not sent with success are counted by this counter. any initial collided transmission attempts before a successful frame transmission do not add to this counter. port_index + 0x41 r 0x00000000 txucpkts the total number of unicast packets transmitted (excluding bad packets). port_index + 0x42 r 0x00000000 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 172 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 txmcpkts the total number of multicast packets transmitted (excluding bad packets). note: this count includes pause control packets, which are also counted in the txpauseframes counter. thus, these types of packets are counted twice. take care when summing register counts for reporting mib information. port_index + 0x43 r 0x00000000 txbcpkts the total number of broadcast packets transmitted (excluding bad packets). port_index + 0x44 r 0x00000000 txpkts64octets the total number of packets transmitted (including bad packets) that were 64 octets in length. incremented for tagged packets with a length of 64 bytes, including tag field. port_index + 0x45 r 0x00000000 txpkts65to127octets the total number of packets transmitted (including bad packets) that were 65-127 octets in length. incremented for tagged packets with a length of 65-127 bytes, including tag field . port_index + 0x46 r 0x00000000 txpkts128to255octets the total number of packets transmitted (including bad packets) that were 128-255 octets in length. incremented for tagged packets with a length of 128-255 bytes, including tag field. port_index + 0x47 r 0x00000000 txpkts256to511octets the total number of packets transmitted (including bad packets) that were 256-511 octets in length. incremented for tagged packets with a length of 256-511 bytes, including tag field. port_index + 0x48 r 0x00000000 txpkts512to1023octets the total number of packets transmitted (including bad packets) that were 512-1023 octets in length. incremented for tagged packets with a length of 512-1023 bytes, including tag field . port_index + 0x49 r 0x00000000 txpkts1024to1518octets the total number of packets transmitted (including bad packets) that were 1024-1518 octets in length. incremented for tagged packet with a length between 1024-1522, including the tag. port_index + 0x4a r 0x00000000 txpkts1519tomaxoctets the total number of packets transmitted (including bad packets) that were greater than 1518 octets in length. incremented for tagged packet with a length between 1523 - max fame size, including the tag. port_index + 0x4b r 0x00000000 table 94 mac tx statistics ($ port_index +0x40 ? +0x58) (sheet 2 of 4) name description address type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 173 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 txdeferred number of times the initial transmission attempt of a frame is postponed due to another frame already being transmitted on the ethernet network. txtotalcollisions. note: na - half-duplex only port_index + 0x4c r 0x00000000 txtotalcollisions sum of all collision events. note: na - half-duplex only port_index + 0x4d r 0x00000000 txsinglecollisions a count of successfully transmitted frames on a particular interface where the transmission is in hibited by exactly one collision. a frame that is counted by an instance of this object is also counted by the corresponding instance of either the unicastpkts, multicastpkts, or broadcastpkts, and is not counted by the corresponding instance of the multiplecollisionframes object. note: na - half-duplex only port_index + 0x4e r 0x00000000 txmultiplecollisions a count of successfully transmitted frames on a particular interface for which transmission is inhibited by more than one collision. a frame that is counted by an instance of this object is also counted by the corresponding instance of either the unicastpkts, multicastpkts, or broadcastpkts, and is not counted by the corresponding instance of the singlecollisionframes object. note: na - half-duplex only port_index + 0x4f r 0x00000000 txlatecollisions the number of times a collision is detected on a particular interface later than 512 bit-times into the transmission of a packet. such frame are terminated and discarded. note: na - half-duplex only port_index + 0x50 r 0x00000000 txexcessivecollisionerrors a count of frames, which collides 16 times and is then discarded by the mac. not effecting xmultiplecollisions note: na - half-duplex only port_index + 0x51 r 0x00000000 txexcessivedeferralerrors number of times frame transmission is postponed more than 2*maxframesize because of another frame already being transmitted on the ethernet network. this causes the mac to discard the frame. note: na - half-duplex only port_index + 0x52 r 0x00000000 txexcessivelengthdrop frame transmissions aborted by the mac because the frame is longer than maximum frame size. these frames are truncated by the mac when the maximum frame size violation is detected by the mac. port_index + 0x53 r 0x00000000 table 94 mac tx statistics ($ port_index +0x40 ? +0x58) (sheet 3 of 4) name description address type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 174 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 8.4.4 phy autoscan registers note: these register hold the current values of the phy registers only when autoscan (see section 5.5.8, autoscan operation , on page 102 ) is enabled and the ixf1104 mac is configured in copper mode. these registers are not applicable in fiber mode. txunderrun internal tx error that causes the mac to end the transmission before the end of the frame because the mac did not get the needed data in time for transmission. the frames are lost and a fragment or a crc error is transmitted. port_index + 0x54 r 0x00000000 txtagged number of ok frames with vlan tag. (type field = 0x8100). port_index + 0x55 r 0x00000000 txcrcerror number of frames transmitted with a legal size but with the wrong crc field (also called fcs field). port_index + 0x56 r 0x00000000 txpauseframes number of pause mac frames transmitted. port_index + 0x57 r 0x00000000 txflowcontrolcollisions send intentionally generates collisions to curb reception of incoming traffic due to insufficient memory available for additional frames. the port must be in half-duplex mode with flow control enabled. note: to receive a correct statistic, a last frame may have to be transmitted after the last flow control collisions send. note: na - half-duplex only port_index + 0x58 r 0x00000000 table 94 mac tx statistics ($ port_index +0x40 ? +0x58) (sheet 4 of 4) name description address type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 95 phy control ($ port index + 0x60) (sheet 1 of 2) bit name description type 1 default 0x00000010 001000 31:16 reserved reserved ro 0x0000 15 reset phy soft reset. resets the phy registers to their default value. this register bit self-clears after the reset is complete. 0 = normal operation 1 = phy reset ro 0 14 loopback 0 = disable loopback mode 1 = enable loopback mode ro 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. this register is ignored if auto-negotiation is enabled. page 175 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 13 speed selection 0.6 (speed<1> 0.13 (speed<0>) 00 = 10 mbps 01 = 100 mbps 10 = 1000 mbps (manual mode not allowed) 11 = reserved ro 0 2 12 auto-negotiation enable 0 = disable auto-negotiation process 1 = enable auto-negotiation process this register bit must be enabled for 1000base-t operation. ro 1 11 power-down 0 = normal operation 1 = power-down ro 0 10 isolate 0 = 1 = electrically isolate phy from gmii ro 0 9 restart auto-negotiation 0 = normal operation 1 = restart auto-negotiation process ro 0 8 duplex mode 0 = half-duplex mode 1 = full-duplex mode ro 1 2 7 collision test 0 = disable col signal test 1 = enable col signal test this register bit is ignored unless loopback is enabled (register bit 0.14 = 1) ro 0 6 speed selection 1000 mbps 0.6 (speed<1>) 0.13 (speed<0>) 00 = 10 mbps 01 = 100 mbps 10 = 1000 mbps (manual mode now allowed) 11 = reserved ro 0 2 5:0 reserved reserved ro 0 table 95 phy control ($ port index + 0x60) (sheet 2 of 2) bit name description type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write 2. this register is ignored if auto-negotiation is enabled. table 96 phy status ($ port index + 0x61) (sheet 1 of 2) bit name description type 1 default 0x001111001 00001001 31:16 reserved reserved ro 0 15 100base-t4 0 = phy not able to operate in 100base-t4 1 = phy able to operate in 100base-t4 ro 0 14 100base-x full-duplex 0 = phy not able to operate in 100base-x in full- duplex mode 1 = phy able to operate in 100base-x in full- duplex mode ro 1 13 100base-x half-duplex 0 = phy not able to operate in 100base-x in half- duplex mode 1 = phy able to operate in 100base-x in half- duplex mode ro 1 1. r = read only; rr = clear on read; w = write; r/w = read/write page 176 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 12 10 mbps full-duplex 0 = phy not able to operate in 10 mbps in full- duplex mode 1 = phy able to operate in 10 mbps in full-duplex mode ro 1 11 10 mbps half-duplex 0 = phy not able to operate in 10 mbps in half- duplex mode 1 = phy able to operate in 10 mbps in half-duplex mode ro 1 10 100base-t2 full-duplex 0 = phy not able to operate in 10base-t2 in full- duplex mode (not supported) 1 = phy able to operate in 100base-t2 in full- duplex mode ro 0 9 100base-t2 half-duplex 0 = phy not able to operate in 100base-t2 in half-duplex mode 1 = phy able to operate in 100base-t2 in half- duplex mode ro 0 8 extended status 0 = no extended status information in register 15 1 = extended status information in register 15 ro 1 7 reserved reserved ro 0 6 mf preamble suppression 0 = phy will not accept management frames with preamble suppressed 1 = phy will accept management frames with preamble suppressed ro 0 5 reserved reserved ro 0 4 remote fault 0 = 1 = remote fault condition detected ro 0 3 auto-negotiation ability 0 = 1 = phy is able to perform auto-negotiation ro 1 2link status 0 = link is down 1 = link is up ro 0 1 jabber detect 0 = jabber condition not detected 1 = jabber condition detected ro 0 0 extended capability 0 = no extended register capabilities 1 = extended register capabilities ro 1 table 96 phy status ($ port index + 0x61) (sheet 2 of 2) bit name description type 1 default 1. r = read only; rr = clear on read; w = write; r/w = read/write table 97 phy identification 1 ($ port index + 0x62) bit name description type 1 default 0x00013 31:16 reserved reserved ro 0 15:0 phy id number the phy identifier is composed of register bits 18.3 of the oui (organizationally unique identifier) ro h0013 1. ro = read only; rr = clear on read; w = write; r/w = read/write page 177 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 98 phy identification 2 ($ port index + 0x63) bit name description type 1 default 0x001111001 00000000 31:16 reserved reserved ro 0 15:10 phy id number the phy identifier is composed of register bits 24:19 of the oui (organizationally unique identifier) ro 011110 9:4 manufacturer?s model six bits containing the manufacturer?s part number ro 010000 3:0 manufacturer?s revision number four bits containing the manufacturer?s revision number ro 0000 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 99 auto-negotiation advertisemen t ($ port index + 0x64) (sheet 1 of 2) bit name description type 1 default 0x00000100 111100001 31:16 reserved reserved ro 0 15 next page 0 = 1 = manual control of next page (software) ro 0 14 reserved reserved ro 0 13 remote fault 0 = no remote fault 1 = remote fault ro 0 12 reserved reserved ro 0 11 asm_dir advertise asymmetric pause direction register bit. this register bit is used in conjunction with pause (register bit 4.10) 0 = link partner is not capable of asymmetric pause 1 = link partner is capable of asymmetric pause ro 1 10 pause advertise to link partner that pause operation is desired (ieee 802.3x standard) ro 0 9 100base-t4 0 = 100base-t4 capability is not available 1 = 100base-t4 capability is available the ixf1104 mac does not support 100base-t4, but allows this register bit to be set to advertise in auto-negotiation sequence for 100base-t4 operation. if this capability is desired, an external 100base-t4 transceiver can be switched in. ro 0 8 100base-tx full-duplex 0 = dte is not 100base-tx, full-duplex mode capable 1 = dte is 100base-tx, full-duplex mode capable ro 1 7 100base-tx half-duplex 0 = dte is not 100base-tx, half-duplex mode capable 1 = dte is 100base-tx, half-duplex mode capable ro 1 1. ro = read only; rr = clear on read; w = write; r/w = read/write page 178 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 6 10base-t full-duplex 0 = dte is not 10base-t, full-duplex mode capable 1 = dte is 10base-t, full-duplex mode capable ro 1 5 10base-t half-duplex 0 = dte is not 10base-t, half-duplex mode capable 1 = dte is 10base-t, half-duplex mode capable ro 1 4:0 selector field, s[4:0] 00001 =ieee 802.3 00010 =ieee 802.9 islan-16t reserved for future auto-negotiation development 11111 = reserved for future auto-negotiation development unspecified or reserved combinations should not be transmitted setting this field to a value other than 00001 will most likely cause auto-negotiation to fail ro 00001 table 99 auto-negotiation advertisemen t ($ port index + 0x64) (sheet 2 of 2) bit name description type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 100 auto-negotiation link partner ba se page ability ($ port index + 0x65) (sheet 1 of 2) bit name description type 1 default 0x0--- 01001111000 01 31:16 reserved reserved ro 0 15 next page 0 = link partner has no ability to send multiple pages 1 = link partner has the ability to send multiple pages ro na 14 acknowledge 0 = link partner has not received link code word from the ixf1104 mac 1 = link partner has received link code word from the ixf1104 mac ro na 13 remote fault 0 = no remote fault 1 = remote fault ro na 12 reserved reserved ro 0 11 asm_dir advertise asymmetric p ause direction register bit. this register bit is used in conjunction with pause (register bit 4.10) 0 = link partner is not capable of asymmetric pause 1 = link partner is capable of asymmetric pause ro 1 10 link partner pause link partner wants to ut ilize pause operation as defined in ieee 802.3x standard ro 0 9 1000base-t4 0 = link partner is not 100base-t4 capable 1 = link partner is 100base-t4 capable ro 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write page 179 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 8 100base-tx full-duplex 0 = link partner is not 100base-tx, full-duplex mode capable 1 = link partner is 100base-tx, full-duplex mode capable ro 1 7 100base-tx half-duplex 0 = link partner is not 100base-tx, half-duplex mode capable 1 = link partner is 100base-tx, half-duplex mode capable ro 1 6 10base-t full-duplex 0 = link partner is not 10base-t, full-duplex mode capable 1 = link partner is 10base-t, full-duplex mode capable ro 1 5 10base-t half-duplex 0 = link partner is not 10base-t, half-duplex mode capable 1 = link partner is 10base-t, half-duplex mode capable ro 1 4:0 selector field, s[4:0] 00001 =ieee 802.3 00010 =ieee 802.9 islan-16t 00000 =reserved for future auto-negotiation development 11111 = reserved for future auto-negotiation development unspecified or reserved combinations should not be transmitted setting this field to a value other than 00001 will most likely cause auto-negotiation to fail ro 00001 table 100 auto-negotiation link partner ba se page ability ($ port index + 0x65) (sheet 2 of 2) bit name description type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 101 auto-negotiation expansion ($ port index + 0x66) (sheet 1 of 2) bit name description type 1 default 0x0000000 31:6 reserved reserved ro 0 5 base page this register bit indicates the status of the auto- negotiation variable, base page. it flags synchronization with the auto-negotiation state diagram allowing detection of interrupted links. this register bit is only used if register bit 16.1 (alternate next page feature) is set. 0 = base_page = false 1 = base_page = true ro 0 4 parallel detection fault 0 = parallel detection fault has not occurred 1 = parallel detection fault has occurred ro 0 3 link partner next page able 0 = link partner is not next page able 1 = link partner is next page able ro 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write page 180 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 8.4.5 global status and configuration register overview table 103 through table 112, jtag id ($0x50c) , on page 185 provide an overview for the global control and status registers. 2 next page able 0 = local device is not next page able 1 = local device is next page able ro 0 1 page received indicates that a new page has been received and the received code word has been loaded into register 5 (base pages) or register 8 (next pages) as specified in the eee 802.3 standard. this bit clears on read. ro 0 0 link partner auto- negotiation able 0 = link partner is not auto-negotiation able 1 = link partner is auto-negotiation able ro 0 table 101 auto-negotiation ex pansion ($ port index + 0x 66) (continued) (sheet 2 of 2) bit name description type 1 default 1. ro = read only; rr = clear on read; w = write; r/w = read/write table 102 auto-negotiation next page transmit ($ port index + 0x67) bit name description type 1 default 0x0000000 31:16 reserved reserved ro 0 15 next page (np) 0 = last page 1 = additional next pages follow ro 0 14 reserved reserved ro 0 13 message page (mp) 0 = unformatted page 1 = message page ro 0 12 acknowledge 2 0 = cannot comply with message 1 = complies with message ro 0 11 toggle (t) 0 = previous value of the transmitted link code word was logic one 1 = previous value of the transmitted link code word was logic zero ro 0 10:0 message/unformatted code field 11-bit message code field see ieee 802.3 annex 28c ro 0 1. ro = read only; rr = clear on read; w = write; r/w = read/write page 181 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 103 port enable ($0x500) bit name description type * default register description: a control register for each port in the ixf1104 mac. port id = bit position in the register. to make a port active, the bit must be set high. for example, port 2 active implies a register value of 0000.0100. setting the bit to 0 de-asserts the enable. the default state for this register is for all four ports to be disabled. 0x00000000 31:4 reserved reserved ro 0x0000000 3 port 3 enable port 3 0 = disable 1 = enable r/w 0 2 port 2 enable port 2 0 = disable 1 = enable r/w 0 1 port 1 enable port 1 0 = disable 1 = enable r/w 0 0 port 0 enable port 0 0 = disable 1 = enable r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 104 interface mode ($0x501) bit name description type 1 default register description: if_mode ? four bits of this register determines the phy interface mode. 0 = fiber (serdes/omi interface) 1 = copper (gmii or rgmii interface) changes to the data setting of this regist er must be made in conjunction with the clock and interface mode change enable ports 0 - 3 ($0x794) to ensure a safe transition to a new operational mode (see section 6.1, change port mode initialization sequence , on page 127 ). the enable clock mode change bit has to be set bac k to 1 after the configuration change takes effect. 0x00000000 31:4 reserved reserved ro 0x0000000 3 port 3 interface mode 0 = fiber mode 1 = copper mode r/w 0 2 port 2 interface mode 0 = fiber mode 1 = copper mode r/w 0 1 port 1 interface mode 0 = fiber mode 1 = copper mode r/w 0 0 port 0 interface mode 0 = fiber mode 1 = copper mode r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 182 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 105 link led enable ($0x502) bit name description type 1 default register description: per port bit should be set upon detection of link to enable proper operation of the link leds. 0x00000000 31:4 reserved reserved r/w 0x00000 3 link led enable port 3 port 3 link 0 = no link 1 = link r/w 0 2 link led enable port 2 port 2 link 0 = no link 1 = link r/w 0 1 link led enable port 1 port 1 link 0 = no link 1 = link r/w 0 0 link led enable port 0 port 0 link 0 = no link 1 = link r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 106 mac soft reset ($0x505) bit name description type 1 default register description: per-port software-activated reset of the mac core. 0x00000000 31:4 reserved reserved r/w 0x00000 3 software reset mac 3 port 3 0 = reset inactive 1 = enable r/w 0 2 software reset mac 2 port 2 0 = reset inactive 1 = enable r/w 0 1 software reset mac 1 port 1 0 = reset inactive 1 = enable r/w 0 0 software reset mac 0 port 0 0 = reset inactive 1 = enable r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 183 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 107 mdio soft reset ($0x506) bit name description type 1 default register description: software-activated reset of the mdio module. 0x00000000 31:1 reserved reserved ro 0x00000000 0 software mdio reset 0 = reset inactive 1 = reset active r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 108 cpu interface ($0x508) bit name description type 1 default register description: cpu interface endian select. allows the user to select the endian of the cpu interface to allow for various cpus to be connected to the ixf1104 mac. 0x00000000 31:25 reserved reserved ro 0x00 24 cpu endian reserved in little endian valid in big endian 0 = little endian 1 = big endian r/w 0 23:1 reserved reserved ro 0x000000 0 cpu endian control reserved in big endian valid in little endian 0 = little endian 1 = big endian r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write note: since the endianess of the bus is unknown when writ ing to this register, write 0x01000001 to set the bit and 0x0 to clear it. table 109 led control ($0x509) bit name description type 1 default register description: global selection of led mode. 0x00000000 31:2 reserved reserved ro 0x00000000 1 led enable 0 = disable led block 1 = enable led block r/w 0 0 led control 0 = enable led mode 0 for use with sgs thomson m5450 led driver (default) 1 = led mode 1 for use with standard octal shift register r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 184 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 110 led flash rate ($0x50a) bit name description type 1 default register description: global selection of led flash rate. 0x00000000 31:3 reserved reserved ro 0x00000000 2:0 led flash rate control 000 =100 ms flash rate 001 =200 ms flash rate 010 =300 ms flash rate 011 = 400 ms flash rate 100 =500 ms flash rate 101 =reserved 110 = reserved 111 = reserved r/w 000 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 111 led fault disable ($0x50b) bit name description type 1 default register description: per-port fault disable. disables t he led flashing for local or remote faults. 0x00000000 31:4 reserved reserved ro 0x0000000 3 led port 3 fault control port 3 0 = fault enabled 1 = fault disabled r/w 0 2 led port 2 fault control port 2 0 = fault enabled 1 = fault disabled r/w 0 1 led port 1 fault control port 1 0 = fault enabled 1 = fault disabled r/w 0 0 led port 0 fault control port 0 0 = fault enabled 1 = fault disabled r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 185 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 8.4.6 rx fifo register overview table 113 through table 131 provide an overview of the rx fifo registers, which include the rx fifo high and low watermarks. table 112 jtag id ($0x50c) bit name description type 1 default register description: the value of this register foll ows the same scheme as the device identification register found in the ieee 1149.1 s pecification. the upper four bits correspond to silicon stepping. the next 16 bits store a part id number. the next 11 bits contain a jedec manufacturer id. bit zero = 1 if the chip is the first in a stack. the encoding scheme used for the product id field is implementation-dependent. 0x10450013 31:28 version version ro 0001 2 27:12 part id part id ro 0000010001 010000 11:8 jedec continuation characters jedec continuation characters ro 0000 7:1 jedec id jedec id ro 0001001 0fixed fixed ro 1 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write 2. these bits vary with stepping. table 113 rx fifo high watermark port 0 ($0x580) bit name description type 1 default register description: the default value of 0x0e6 represents 230 eight-byte locations. this equates to 1840 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the rx fifo exc eeds the high watermark, flow control is automatically initiated within the mac to avoid an overflow condition. 0x0e6 31:12 reserved reserved ro 0x00000 11: 0 rx fifo high watermark port 0 the high water mark value. note: must be greater than the rx fifo low watermark and rx fifo transfer threshold. r/w 0x0e6 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 186 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 114 rx fifo high watermark port 1 ($0x581) bit name description type 1 default register description: the default value of 0x0e6 represents 230 eight-byte locations. this equates to 1840 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the rx fifo exc eeds the high watermark, flow control is automatically initiated within the mac to avoid an overflow condition. 0x0e6 31:12 reserved reserved ro 0x00000 11: 0 rx fifo high watermark port 1 the high water mark value. note: must be greater than the rx fifo low watermark and rx fifo transfer threshold. r/w 0x0e6 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 115 rx fifo high watermark port 2 ($0x582) bit name description type 1 default register description: the default value of 0x0e6 represents 230 eight-byte locations. this equates to 1840 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the rx fifo exc eeds the high watermark, flow control is automatically initiated within the mac to avoid an overflow condition. 0x0e6 31:12 reserved reserved ro 0x00000 11: 0 rx fifo high watermark port 2 the high water mark value. note: must be greater than the rx fifo low watermark and rx fifo transfer threshold. r/w 0x0e6 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 116 rx fifo high watermark port 3 ($0x583) bit name description type 1 default register description: the default value of 0x0e6 represents 230 eight-byte locations. this equates to 1840 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the rx fifo exc eeds the high watermark, flow control is automatically initiated within the mac to avoid an overflow condition. 0x0e6 31:12 reserved reserved ro 0x00000 11: 0 rx fifo high watermark port 3 the high water mark value. note: must be greater than the rx fifo low watermark and rx fifo transfer threshold. r/w 0x0e6 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 187 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 117 rx fifo low watermark port 0 ($0x58a) bit name description type 1 default register description: the default value of 0x072 represents 114 eight-byte locations. this equates to 912 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the rx fifo falls below the low watermark, flow control is automatically de-asserted within the mac to al low more line-side data to be captured by the rx fifo. 0x072 31:12 reserved reserved ro 0x00000 11: 0 rx fifo low watermark port 0 the high watermark value note: should never be greater or equal to the high watermark. r/w 0x072 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 118 rx fifo low watermark port 1 ($0x58b) bit name description type 1 default register description: the default value of 0x072 represents 114 eight-byte locations. this equates to 912 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the rx fifo falls below the low watermark, flow control is automatically de-asserted within the mac to al low more line-side data to be captured by the rx fifo. 0x072 31:12 reserved reserved ro 0x00000 11: 0 rx fifo low watermark port 1 the high watermark value note: should never be greater or equal to the high watermark. r/w 0x072 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 119 rx fifo low watermark port 2 ($0x58c) bit name description type 1 default register description: the default value of 0x072 represents 114 eight-byte locations. this equates to 912 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the rx fifo falls below the low watermark, flow control is automatically de-asserted within the mac to al low more line-side data to be captured by the rx fifo. 0x072 31:12 reserved reserved ro 0x00000 11: 0 rx fifo low watermark port 2 the high watermark value note: should never be greater or equal to the high watermark. r/w 0x072 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 188 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 120 rx fifo low watermark port 3 ($0x58d) bit name description type 1 default register description: the default value of 0x072 represents 114 eight-byte locations. this equates to 912 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the rx fifo falls below the low watermark, flow control is automatically de-asserted within the mac to al low more line-side data to be captured by the rx fifo. 0x072 31:12 reserved reserved ro 0x00000 11: 0 rx fifo low watermark port 3 the high watermark value note: should never be greater or equal to the high watermark. r/w 0x072 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 121 rx fifo overflow frame drop counter ports 0 - 3 ($0x594 ? 0x597) name description address type 1 default rx fifo overflow frame drop counter on port 0 when rx fifo on port 0 becomes full or reset, the number of frames lost/dropped on this port are shown in this register. 0x594 r 0x00000000 rx fifo overflow frame drop counter on port 1 when rx fifo on port 1 becomes full or reset, the number of frames lost/dropped on this port are shown in this register. 0x595 r 0x00000000 rx fifo overflow frame drop counter on port 2 when rx fifo on port 2 becomes full or reset, the number of frames lost/dropped on this port are shown in this register. 0x596 r 0x00000000 rx fifo overflow frame drop counter on port 3 when rx fifo on port 3 becomes full or reset, the number of frames lost/dropped on this port are shown in this register. 0x597 r 0x00000000 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 122 rx fifo port reset ($0x59e) (sheet 1 of 2) bit name description type 1 default register description: the soft reset register for each port in the rx block. port id = bit position in the register. to make the reset active, the bit must be set high. for example, reset of port 1 implies register value = 0000_0018. setting the bit to 0 de-asserts the reset. 0x00000000 31:4 reserved reserved ro 0x0000000 3 reset rx fifo for port 3 port 3 0 = de-assert reset 1 = reset r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 189 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 2 reset rx fifo for port 2 port 2 0 = de-assert reset 1 = reset r/w 0 1 reset rx fifo for port 1 port 1 0 = de-assert reset 1 = reset r/w 0 0 reset rx fifo for port 0 port 0 0 = de-assert reset 1 = reset r/w 0 table 122 rx fifo port reset ($0x59e) (sheet 2 of 2) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 123 rx fifo errored frame drop enable ($0x59f) bit name description type 1 default register description: this register configures t he dropping of error packets (debad). note: jumbo packets are not dropped. 0x00000000 31:4 reserved reserved ro 0x0000000 3 rx fifo errored frame drop enable port 3 this bit is used in conjunc tion with mac filter bits. this allows the user to select whether the errored packets are to be dropped or not. 1 = frame drop enable 0 = frame drop disable r/w 0 2 rx fifo errored frame drop enable port 2 this bit is used in conjunc tion with mac filter bits. this allows the user to select whether the errored packets are to be dropped or not. 1 = frame drop enable 0 = frame drop disable r/w 0 1 rx fifo errored frame drop enable port 1 this bit is used in conjunc tion with mac filter bits. this allows the user to select whether the errored packets are to be dropped or not. 1 = frame drop enable 0 = frame drop disable r/w 0 0 rx fifo errored frame drop enable port 0 this bit is used in conjunc tion with mac filter bits. this allows the user to select whether the errored packets are to be dropped or not. 1 = frame drop enable 0 = frame drop disable r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 190 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 124 rx fifo overflow event ($0x5a0) bit name description type 1 default register description: this register provides a status if a fifo-full situation occurs (for example, a fifo overflow). the bit position equals the port number. this register is cleared on read. 0x00000000 31:4 reserved reserved ro 0x0000000 3 rx fifo overflow event on port 3 port 3 0 = fifo overflow event did not occur 1 = fifo overflow event occurred r0 2 rx fifo overflow event on port 2 port 2 0 = fifo overflow event did not occur 1 = fifo overflow event occurred r0 1 rx fifo overflow event on port 1 port 1 0 = fifo overflow event did not occur 1 = fifo overflow event occurred r0 0 rx fifo overflow event on port 0 port 0 0 = fifo overflow event did not occur 1 = fifo overflow event occurred r0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 191 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 125 rx fifo errored frame drop counter ports 0 - 3 ($0x5a2 - 0x5a5) name description address type default rx fifo errored frame drop counter on port 0 this register counts all frames dropped from the rx fifo for port 0 by meeting one of the following conditions: ? frames are removed in conjunction with the section 123, rx fifo errored frame drop enable ($0x59f) and the section 91, rx packet filter control ($ port_index + 0x19) . ? frames are greater than the section 81, max frame size (addr: port_index + 0x0f) . this register is cleared on read. 0x5a2 r 0x00000000 rx fifo errored frame drop counter on port 1 this register counts all frames dropped from the rx fifo for port 1 by meeting one of the following conditions: ? frames are removed in conjunction with the section 123, rx fifo errored frame drop enable ($0x59f) and the section 91, rx packet filter control ($ port_index + 0x19) . ? frames are greater than the section 81, max frame size (addr: port_index + 0x0f) . this register is cleared on read. 0x5a3 r 0x00000000 rx fifo errored frame drop counter on port 2 this register counts all frames dropped from the rx fifo for port 2 by meeting one of the following conditions: ? frames are removed in conjunction with the section 123, rx fifo errored frame drop enable ($0x59f) and the section 91, rx packet filter control ($ port_index + 0x19) . ? frames are greater than the section 81, max frame size (addr: port_index + 0x0f) . this register is cleared on read. 0x5a4 r 0x00000000 rx fifo errored frame drop counter on port 3 this register counts all frames dropped from the rx fifo for port 3 by meeting one of the following conditions: ? frames are removed in conjunction with the section 123, rx fifo errored frame drop enable ($0x59f) and the section 91, rx packet filter control ($ port_index + 0x19) . ? frames are greater than the section 81, max frame size (addr: port_index + 0x0f) . this register is cleared on read. 0x5a5 r 0x00000000 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 192 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 126 rx fifo spi3 loopback enable for ports 0 - 3 ($0x5b2) bit name description type 1 default register description: enables the tx spi3 port to send packets into the rx_fifo instead of into the tx fifo, creating a spi3 loopback. 0x00000000 31:12 reserved reserved ro 0x00000 11 spi3 loopback enable for port 3 0 = disabled 1 = enabled r/w 0x0 10 spi3 loopback enable for port 2 0 = disabled 1 = enabled r/w 0x0 9 spi3 loopback enable for port 1 0 = disabled 1 = enabled r/w 0x0 8 spi3 loopback enable for port 0 0 = disabled 1 = enabled r/w 0x0 7:0 reserved write as 0, ignore on read. r/w 0x00 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 127 rx fifo padding and crc strip enable ($0x5b3) (sheet 1 of 2) bit name description type 1 default register description: this control register enables to pre-pend every packet with two extra bytes and also enables the crc stripping of a packet. 0x00000000 31:8 reserved reserved ro 0x000000 7 crc stripping enable for port 3 crc stripping is enabled for port 3. 0 = disabled 1 = enabled r/w 0 6 crc stripping enable for port 2 crc stripping is enabled for port 2. 0 = disabled 1 = enabled r/w 0 5 crc stripping enable for port 1 crc stripping is enabled for port 1. 0 = disabled 1 = enabled r/w 0 4 crc stripping enable for port 0 crc stripping is enabled for port 0. 0 = pre-pending disabled 1 = pre-pending enabled r/w 0 3 pre-pending enable 2 port 3 enables pre-pending of two bytes at the start of every packet ? port 3. 0 = disabled 1 = enabled r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write 2. pre-pending should not be enabled in loopback mode. page 193 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 2 pre-pending enable 2 port 2 enables pre-pending of two bytes at the start of every packet ? port 2. 0 = disabled 1 = enabled r/w 0 1 pre-pending enable 2 port 1 enables pre-pending of two bytes at the start of every packet ? port 1. 0 = disabled 1 = enabled r/w 0 0 pre-pending enable 2 port 0 enables pre-pending of two bytes at the start of every packet ? port 0. 0 = disabled 1 = enabled r/w 0 table 127 rx fifo padding and crc strip enable ($0x5b3) (sheet 2 of 2) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write 2. pre-pending should not be enabled in loopback mode. table 128 rx fifo transfer threshold port 0 ($0x5b8) bit name description type default register description: rx fifo transfer threshold for port 0 in 8-byte location. 0x000000be 31:12 reserved reserved ro 0x00000 11:0 rx fifo transfer threshold - port 0 rx fifo transfer threshold for port 0. this must be less than the rx fifo high water mark. user definable control register that sets the threshold where a packet starts transitioning to the spi3 interface from the rx fifo before the eop is received. packets received in the rx fifo below this threshold are treated as store and forward. note: do not program the rx fifo transfer threshold below a setting of 0xbe (1520bytes). r/w 0x0be 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 129 rx fifo transfer threshold port 1 ($0x5b9) (sheet 1 of 2) bit name description type default register description: rx fifo transfer threshold fo r port 1in 8-byte location. 0x000000be page 194 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 31:12 reserved reserved ro 0x00000 11:0 rx fifo transfer threshold - port 1 rx fifo transfer threshold for port 1. this must be less than the rx fifo high watermark. user definable control register that sets the threshold where a packet starts transitioning to the spi3 interface from the rx fifo before the eop is received. packets received in the rx fifo below this threshold are treated as store and forward. note: do not program the rx fifo transfer threshold below a setting of 0xbe (1520bytes). r/w 0x0be 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 129 rx fifo transfer threshold port 1 ($0x5b9) (sheet 2 of 2) table 130 rx fifo transfer threshold port 2 ($0x5ba) bit name description type default register description: rx fifo transfer threshold for port 2 in 8-byte location. 0x000000be 31:12 reserved reserved ro 0x00000 11:0 rx fifo transfer threshold - port 2 rx fifo transfer threshold for port 2. this must be less than the rx fifo high water mark. user definable control register that sets the threshold where a packet starts transitioning to the spi3 interface from the rx fifo before the eop is received. packets received in the rx fifo below this threshold are treated as store and forward. note: do not program the rx fifo transfer threshold below a setting of 0xbe (1520bytes). r/w 0x0be 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 131 rx fifo transfer threshold port 3 ($0x5bb) bit name description type default register description: rx fifo transfer threshold for port 3 in 8-byte location. 0x000000be 31:12 reserved reserved ro 0x00000 11:0 rx fifo transfer threshold - port 3 rx fifo transfer threshol d for port 3. this must be less than the rx fifo high water mark. user definable control register that sets the threshold where a packet starts transitioning to the spi3 interface from the rx fifo before the eop is received. packets received in the rx fifo below this threshold are treated as store and forward. note: do not program the rx fifo transfer threshold below a setting of 0xbe (1520bytes). r/w 0x0be 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 195 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 8.4.7 tx fifo register overview table 132 through table 139 provide an overview of the tx fifo registers, which include the tx fifo high and low watermark. table 132 tx fifo high watermark ports 0 - 3 ($0x600 ? 0x603) name description address type 1 default tx fifo high watermark port 0 high watermark for tx fifo port 0. the default value of 0x3e0 represents 992 8-byte locations. this equates to 7936 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the tx fifo exceeds the high watermark, flow control is automatically initiated on the spi3 interface to request that the switch fabric stops data transfers to avoid an overflow condition. 0x600 r/w 0x000003e0 tx fifo high watermark port 1 high watermark for tx fifo port 1. the default value of 0x3e0 represents 992 8-byte locations. this equates to 7936 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the tx fifo exceeds the high watermark, flow control is automatically initiated on the spi3 interface to request that the switch fabric stops data transfers to avoid an overflow condition. 0x601 r/w 0x000003e0 tx fifo high watermark port 2 high watermark for tx fifo port 2. the default value of 0x3e0 represents 992 8-byte locations. this equates to 7936 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the tx fifo exceeds the high watermark, flow control is automatically initiated on the spi3 interface to request that the switch fabric stops data transfers to avoid an overflow condition. 0x602 r/w 0x000003e0 tx fifo high watermark port 3 high watermark for tx fifo port 3. the default value of 0x3e0 represents 992 8-byte locations. this equates to 7936 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the tx fifo exceeds the high watermark, flow control is automatically initiated on the spi3 interface to request that the switch fabric stops data transfers to avoid an overflow condition. 0x603 r/w 0x000003e0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 196 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 133 tx fifo low watermark register ports 0 - 3 ($0x60a ? 0x60d) name description address type 1 default tx fifo low watermark port 0 low watermark for tx fifo port 0. the default value of 0x0d0 represents 208 8-byte locations. this equates to 1664 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the tx fifo falls below the low watermark, flow control is automatically de-asserted on the spi3 interface to allow further data to be sent by the switch fabric to the ixf1104 mac. 0x60a r/w 0x000000d0 tx fifo low watermark port 1 low watermark for tx fifo port 1. the default value of 0x0d0 represents 208 8-byte locations. this equates to 1664 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the tx fifo falls below the low watermark, flow control is automatically de-asserted on the spi3 interface to allow further data to be sent by the switch fabric to the ixf1104 mac. 0x60b r/w 0x000000d0 tx fifo low watermark port 2 low watermark for tx fifo port 2. the default value of 0x0d0 represents 208 8-byte locations. this equates to 1664 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the tx fifo falls below the low watermark, flow control is automatically de-asserted on the spi3 interface to allow further data to be sent by the switch fabric to the ixf1104 mac. 0x60c r/w 0x000000d0 tx fifo low watermark port 3 low watermark for tx fifo port 3. the default value of 0x0d0 represents 208 8-byte locations. this equates to 1664 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the tx fifo falls below the low watermark, flow control is automatically de-asserted on the spi3 interface to allow further data to be sent by the switch fabric to the ixf1104 mac. 0x60d r/w 0x000000d0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 197 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 134 tx fifo mac threshold register ports 0 - 3 ($0x614 ? 0x617) name description address type 1 default tx fifo mac threshold port 0 mac threshold for tx fifo port 0. the default value of 0x1be represents 446 8-byte locations. this equates to 3568 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the tx fifo reaches this threshold, data is forwarded to the mac core and line-side interfaces for onward transmission. by setting the threshold to an appropriate value, the user can configure the tx fifo to operate in a ?cut-through? mode rather than the default ?store and forward? operation mode. 0x614 r/w 0x000001be tx fifo mac threshold port 1 mac threshold for tx fifo port 1. the default value of 0x1be represents 446 8-byte locations. this equates to 3568 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the tx fifo reaches this threshold, data is forwarded to the mac core and line-side interfaces for onward transmission. by setting the threshold to an appropriate value, the user can configure the tx fifo to operate in a ?cut-through? mode rather than the default ?store and forward? operation mode. 0x615 r/w 0x000001be tx fifo mac threshold port 2 mac threshold for tx fifo port 2. the default value of 0x1be represents 446 8-byte locations. this equates to 3568 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the tx fifo reaches this threshold, data is forwarded to the mac core and line-side interfaces for onward transmission. by setting the threshold to an appropriate value, the user can configure the tx fifo to operate in a ?cut-through? mode rather than the default ?store and forward? operation mode. 0x616 r/w 0x000001be tx fifo mac threshold port 3 mac threshold for tx fifo port 3. the default value of 0x1be represents 446 8-byte locations. this equates to 3568 bytes of data. a unit entry in this register equates to 8 bytes of data. when the amount of data stored in the tx fifo reaches this threshold, data is forwarded to the mac core and line-side interfaces for onward transmission. by setting the threshold to an appropriate value, the user can configure the tx fifo to operate in a ?cut-through? mode rather than the default ?store and forward? operation mode. 0x617 r/w 0x000001be 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 198 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 135 tx fifo overflow/underflow/out of sequence event ($0x61e) (sheet 1 of 2) bit name description type 1 default register description: tx fifo out of sequence event: these register bits provide status informati on, and indicate if out-of-sequence data has been received. the bit position equals the port number + 8. these bits are cleared on read. 0x0 register description: tx fifo underflow event: this register provides a status that a fifo em pty situation has occurred (for example, a fifo under-run). the bit position equals the port number + 4. this register is cleared on read. 0x0 register description: tx fifo overflow event: this register provides a status that a fifo fu ll situation has occurred (for example, a fifo overflow). the bit position equals the port number. this register is cleared on read. 0x0 31:12 reserved reserved ro 0x00000 11 fose3 port 3 0 = fifo out of sequence event did not occur 1 = fifo out of sequence event occurred r0 10 fose2 port 2 0 = fifo out of sequence event did not occur 1 = fifo out of sequence event occurred r0 9 fose1 port 1 0 = fifo out of sequence event did not occur 1 = fifo out of sequence event occurred r0 8 fose0 port 0 0 = fifo out of sequence event did not occur 1 = fifo out of sequence event occurred r0 7fue3 port 3 0 = fifo underflow event did not occur 1 = fifo underflow event occurred r0 6fue2 port 2 0 = fifo underflow event did not occur 1 = fifo underflow event occurred r0 5fue1 port 1 0 = fifo underflow event did not occur 1 = fifo underflow event occurred r0 4fue0 port 0 0 = fifo underflow event did not occur 1 = fifo underflow event occurred r0 3foe3 port 3 0 = fifo overflow event did not occur 1 = fifo overflow event occurred r0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 199 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 2foe2 port 2 0 = fifo overflow event did not occur 1 = fifo overflow event occurred r0 1foe1 port 1 0 = fifo overflow event did not occur 1 = fifo overflow event occurred r0 0foe0 port 0 0 = fifo overflow event did not occur 1 = fifo overflow event occurred r0 table 135 tx fifo overflow/underflow/out of sequence event ($0x61e) (sheet 2 of 2) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 136 loop rx data to tx fifo (line-side loopback) ports 0 - 3 ($0x61f) bit name description type 1 default register description: this register enables data received fr om the line-side receive interface through the mac to be sent to the tx fifo and back to the line-side transmit interface. 0x00000000 31:4 reserved reserved ro 0x0000000 3 port 3 line-side loopback 0 = disable line-side loopback 1 = enable line-side loopback r/w 0 2 port 2 line-side loopback 0 = disable line-side loopback 1 = enable line-side loopback r/w 0 1 port 1 line-side loopback 0 = disable line-side loopback 1 = enable line-side loopback r/w 0 0 port 0 line-side loopback 0 = disable line-side loopback 1 = enable line-side loopback r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 137 tx fifo port reset ($0x620) (sheet 1 of 2) bit name description type 1 default register description: this is a port reset register for each port in the tx block. port id = bit position in the register. to make the port active, the bit must be set to low. (for example, reset of port 3 implies register value = 1000, setting the bit to 1 asserts the port reset). 0x00000000 31:4 reserved reserved ro 0x0000000 3 port 3 reset port 3 0 = de-assert reset 1 = assert reset r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 200 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 2 port 2 reset port 2 0 = de-assert reset 1 = assert reset r/w 0 1 port 1 reset port 1 0 = de-assert reset 1 = assert reset r/w 0 0 port 0 reset port 0 0 = de-assert reset 1 = assert reset r/w 0 table 137 tx fifo port reset ($0x620) (sheet 2 of 2) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 138 tx fifo overflow frame drop counter ports 0 - 3 ($0x621 ? 0x624) name description address type * default tx fifo overflow frame drop counter on port 0 when tx fifo on port 0 becomes full or reset, the number of frames lost or removed on this port is shown in this register. this register is cleared on read. 0x621 r 0x00000000 tx fifo overflow frame drop counter on port 1 when tx fifo on port 1 becomes full or reset, the number of frames lost or removed on this port is shown in this register. this register is cleared on read. 0x622 r 0x00000000 tx fifo overflow frame drop counter on port 2 when tx fifo on port 2 becomes full or reset, the number of frames lost or removed on this port is shown in this register. this register is cleared on read. 0x623 r 0x00000000 tx fifo overflow frame drop counter on port 3 when tx fifo on port 3 becomes full or reset, the number of frames lost or removed on this port is shown in this register. this register is cleared on read. 0x624 r 0x00000000 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 201 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 139 tx fifo errored frame drop counter ports 0 - 3 ($0x625 ? 0x629) name description address type * default tx fifo errored frame drop counter on port 0 this register provides the number of packets dropped by the tx fifo due to the following: data parity errors short sops (two consecutive sops for a port with no eop) small packets (9-14 bytes) frames received that are signaled with terr on the spi3 tx interface. note: this register is cleared on read. 0x625 r 0x00000000 tx fifo errored frame drop counter on port 1 this register provides the number of packets dropped by the tx fifo due to the following: data parity errors short sops (two consecutive sops for a port with no eop) small packets (9-14 bytes) frames received that are signaled with terr on the spi3 tx interface. note: this register is cleared on read. 0x626 r 0x00000000 tx fifo errored frame drop counter on port 2 this register provides the number of packets dropped by the tx fifo due to the following: data parity errors short sops (two consecutive sops for a port with no eop) small packets (9-14 bytes) frames received that are signaled with terr on the spi3 tx interface. note: this register is cleared on read. 0x627 r 0x00000000 tx fifo errored frame drop counter on port 3 this register provides the number of packets dropped by the tx fifo due to the following: data parity errors short sops (two consecutive sops for a port with no eop) small packets (9-14 bytes) frames received that are signaled with terr on the spi3 tx interface. note: this register is cleared on read. 0x628 r 0x00000000 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 202 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 8.4.8 mdio register overview table 142 through table 145 provide an overview of the mdio registers. table 140 tx fifo occupancy counter for ports 0 - 3 ($0x62d ? 0x630) name description address type default occupancy for tx fifo port 0 this register gives the occupancy for tx fifo port 0. this is a read only register 0x62d r 0x00000000 occupancy for tx fifo port 1 this register gives the occupancy for tx fifo port 1. this is a read only register 0x62e r 0x00000000 occupancy for tx fifo port 2 this register gives the occupancy for tx fifo port 2. this is a read only register 0x62f r 0x00000000 occupancy for tx fifo port 3 this register gives the occupancy for tx fifo port 3. this is a read only register 0x630 r 0x00000000 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 141 tx fifo port drop enable ($0x63d) bit name description type default register description: independently enables the individual tx fifos to drop erroneous packets. 0x0000000f 31:4 reserved reserved ro 0x000000 3 port 3 drop 0 = disable the txfifo from dropping erroneous packets 1 = enable the txfifo to drop erroneous packets r/w 1 2 port 2 drop 0 = disable the txfifo from dropping erroneous packets 1 = enable the txfifo to drop erroneous packets r/w 1 1 port 1 drop 0 = disable the txfifo from dropping erroneous packets 1 = enable the txfifo to drop erroneous packets r/w 1 0 port 0 drop 0 = disable the txfifo from dropping erroneous packets 1 = enable the txfifo to drop erroneous packets r/w 1 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 142 mdio single command ($0x680) (sheet 1 of 2) bit name description type 1 default register description: gives the cpu the ability to perform single mdio read and write accesses to the external phy for por ts that are configured in copper mode. 0x00010000 31:21 reserved reserved ro 00000000000 20 mdio command performs the mdio operation. cleared when done. 0 = mdio ready, operation complete 1 = perform operation r/w 0 19:18 reserved reserved ro 00 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 203 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 17:16 op code mdio op code; two bits identify operation to be performed: 00 = reserved 01 = write operation (as defined in ieee 802.3, clause 22.2.4.5) 10 = read operation (as defined in ieee 802.3, clause 22.2.4.5) 11 = reserved r/w 01 15:10 reserved reserved ro 000000 9:8 phy address sets bits 1:0 of the external phy address. bits 4:2 of the phy address are fixed at 000. r/w 00 7:5 reserved reserved ro 000 4:0 reg address five-bit address to one among 32 registers in an addressed phy device. r/w 00000 table 142 mdio single command ($0x680) (sheet 2 of 2) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 143 mdio single read and write data ($0x681) bit name description type 1 default register description: mdio read and write data. 0x00000000 31:16 mdio read data mdio read dat a from external device. ro 0x0000 15:0 mdio write data mdio write data to external device. r/w 0x0000 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 144 autoscan phy address enable ($0x682) bit name description type 1 default register description: defines valid phy addresses. each bit enables the corresponding phy address. 0 = disable the phy address 1 = enable the phy address note: autoscan is only applicable for the ports in copper mode. 0x00000000 31:4 reserved reserved ro 0x0000000 3:0 autoscan phy address autoscan phy address enable 0 = disable address 1 = enable address r/w 1111 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 204 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 8.4.9 spi3 register overview table 146 through table 148, address parity error packet drop counter ($0x70a) , on page 210 provide an overview of the spi3 registers. table 145 mdio control ($0x683) bit name description type 1 default register description: miscellaneous c ontrol bits. 0x00000000 31:4 reserved reserved ro 0x000 3 mdio in progress mdio progress. this bit reflects the status of mdio transaction 0 = mdio single command not in progress 1 = mdio single command in progress ro 0 2 mdio in progress enable enables the mdio in progress bit 0 = disable mdio in progress register bit 1 = enable mdio in progress register bit r/w 0 1 autoscan enable autoscan enable 0 = disable autoscan 1 = enable autoscan r/w 0 0 mdc speed mdc speed 0 = mdc runs at 2.5 mhz 1 = mdc runs at 18 mhz r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 146 spi3 transmit and global configuration ($0x 700) (sheet 1 of 3) bit name description type 1 default register description: this register gives the configur ation related to the spi3 transmitter and global configuration (4 x 8 mode). 0x00200000 31:24 reserved reserved ro 0x00 23 spi3 transmitter soft reset 1 = the spi3 tx block is reset. r/w 0 22 spi3 receiver soft reset 1 = the spi3 rx block is reset. r/w 0 21 sphy/mphy mode 0 = indicates that spi3 block operates in 32-bit mphy mode. 1 = indicates that the spi3 block operates in 4 x 8 sphy mode. this configuration affects both the spi3 transmitter and receiver functionality. r/w 1 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 205 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 20 tx_ad_prtyer_drop indicates whether to drop packets received with parity error during the address selection phase (tsx and ntenb high) should be dropped. 0 = do not drop packets with address parity error 1 = drop packets with address parity error this is applicable only in mphy mode of operation. this bit is ignored in sphy (4 x 8) mode as there will be no address selection. r/w 0 19 dat_prtyer_drp port 3 sphy/mphy mode: indicates whether to drop packets with data parity error for port 3. 0 = do not drop packets with data parity error (default) 1 = drop packets with data parity error r/w 0x0 18 dat_prtyer_drp port 2 sphy/mphy mode: indicates whether to drop packets with data parity error for port 2. 0 = do not drop packets with data parity error (default) 1 = drop packets with data parity error r/w 0 17 dat_prtyer_drp port 1 sphy/mphy mode: indicates whether to drop packets with data parity error for port 1. 0 = do not drop packets with data parity error (default) 1 = drop packets with data parity error r/w 0 16 dat_prtyer_drp port 0 sphy/mphy mode: indicates whether to drop packets with data parity error for port 0. 0 = do not drop packets with data parity error (default) 1 = drop packets with data parity error r/w 0 15:8 reserved write as 0, ignore on read. r/w 00000000 7 tx_parity_sense port 3 sphy mode: indicates the parity sense to check the parity on tdat bus for port 3. 0 = odd parity 1 = even parity mphy mode: na r/w 0 6 tx_parity_sense port 2 sphy mode: indicates the parity sense to check the parity on tdat bus for port 2. 0 = odd parity 1 = even parity mphy mode: na r/w 0 table 146 spi3 transmit and global configuration ($0x 700) (sheet 2 of 3) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 206 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 5 tx_parity_sense port 1 sphy mode: indicates the parity sense to check the parity on tdat bus for port 1. 0 = odd parity 1 = even parity mphy mode: na r/w 0 4 tx_parity_sense port 0 sphy mode: indicates the parity sense to check the parity on tdat bus for port 0. 0 = odd parity 1 = even parity mphy mode: indicates the parity sense to check the parity on tdat bus for all ports. 0 = odd parity 1 = even parity r/w 0 3 tx_port_enable port 3 sphy mode: 0 = disables the selected spi3tx port 3. 1 = enables the selected spi3 tx port 3. mphy mode: 0 = disables the selected spi3 tx port 3. 1 = enables the selected spi3 tx port 3. r/w 1 2 tx_port_enable port 2 sphy mode: 0 = disables the selected spi3 tx port 2 1 = enables the selected spi3 tx port 2 mphy mode: 0 = disables the selected spi3 tx port 2 1 = enables the selected spi3 tx port 2 r/w 1 1 tx_port_enable port 1 sphy mode: 0 = disables the selected spi3 tx port 1 1 = enables the selected spi3 tx port 1 mphy mode: 0 = disables the selected spi3 tx port 1 1 = enables the selected spi3 tx port 1 r/w 1 0 tx_port_enable port 0 sphy mode: 0 = disables the selected spi3 tx port 0 1 = enables the selected spi3 tx port 0 mphy mode: 0 = disables the selected spi3 tx port 0 1 = enables the selected spi3 tx port 0 r/w 1 table 146 spi3 transmit and global configuration ($0x 700) (sheet 3 of 3) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 207 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 147 spi3 receive configuration ($0x701) (sheet 1 of 3) bit name description type 1 default register description: this register gives the configuration related to the spi3 receiver. 0x00000f80 31:28 reserved reserved ro 0x0 27 b2b_pause port 3 sphy mode: indicates the number of pause cycles to be introduced between back-to-back transfers for port 3. 0 = zero pause cycles 1 = two pause cycles mphy mode: na r/w 0 26 b2b_pause port 2 sphy mode: indicates the number of pause cycles to be introduced between back-to-back transfers for port 2. 0 = zero pause cycles 1 = two pause cycles mphy mode: na r/w 0 25 b2b_pause port 1 sphy mode: indicates the number of pause cycles to be introduced between back-to-back transfers for port 1. 0 = zero pause cycles 1 = two pause cycles mphy mode: na r/w 0 24 b2b_pause port 0 sphy mode: indicates the number of pause cycles to be introduced between back-to-back transfers for port 0. 0 = zero pause cycles 1 = two pause cycles mphy mode: indicates the number of pause cycles to be introduced between back-to-back transfers for all ports. 0 = zero pause cycles 1 = two pause cycles r/w 0 23:22 rx_burst port 3 sphy mode: na mphy mode: na r/w 0x0 21:20 rx_burst port 2 sphy mode: na mphy mode: na r/w 0x0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 208 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 19:18 rx_burst port 1 sphy mode: na mphy mode: na r/w 0x0 17:16 rx_burst port 0 sphy mode: na mphy mode: selects the maximum burst size on the rx path for all ports. 0x = 64 bytes maximum burst size 10 = 128 bytes maximum burst size 11 = 256 bytes maximum burst size r/w 0x0 15 rx_parity_sense port 3 sphy mode: indicates the parity sense to check the parity on rdat bus for port 3. 0 = odd parity 1 = even parity mphy mode: na r/w 0x0 14 rx_parity_sense port 2 sphy mode: indicates the parity sense to check the parity on rdat bus for port 2. 0 = odd parity 1 = even parity mphy mode: na r/w 0x0 13 rx_parity_sense port 1 sphy mode: indicates the parity sense to check the parity on rdat bus for port 1. 0 = odd parity 1 = even parity mphy mode: na r/w 0x0 12 rx_parity_sense port 0 sphy mode: indicates the parity sense to check the parity on rdat bus for port 0. 0 = odd parity 1 = even parity mphy mode: indicates the parity sense to check the parity on rdat bus for all ports. 0 = odd parity 1 = even parity r/w 0x0 table 147 spi3 receive configuration ($0x701) (continued) (sheet 2 of 3) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 209 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 11 rx_port_enable port 3 sphy mode: 0 = disables the selected spi3 rx port. 1 = enables the selected spi3 rx port. mphy mode: 0 = disables the selected spi3 rx port. 1 = enables the selected spi3 rx port. r/w 0x1 10 rx_port_enable port 2 sphy mode: 0 = disables the selected spi3 rx port. 1 = enables the selected spi3 rx port. mphy mode: 0 = disables the selected spi3 rx port. 1 = enables the selected spi3 rx port. r/w 0x1 9 rx_port_enable port 1 sphy mode: 0 = disables the selected spi3 rx port. 1 = enables the selected spi3 rx port. mphy mode: 0 = disables the selected spi3 rx port. 1 = enables the selected spi3 rx port. r/w 0x1 8 rx_port_enable port 0 sphy mode: 0 = disables the selected spi3 rx port. 1 = enables the selected spi3 rx port. mphy mode: 0 = disables the selected spi3 rx port. 1 = enables the selected spi3 rx port. r/w 0x1 7 rx_core_enable sphy mode: na. write as 1, ignore on read. mphy mode: 0 = disables the rx spi3 core. 1 = enables the rx spi3 core. r/w 0x1 6:1 iba[5:0] sphy mode: na. write as 0, ignore on read. mphy mode: sets the 6-bit value appended to the 2-bit address during the port address selection. r/w 0x00 0 rerr_enable sphy mode/mphy mode: frames marked to be filtered (based on the settings in the section 91, rx packet filter control ($ port_index + 0x19) ) or frames above the section 81, max frame size (addr: port_index + 0x0f) that are not dropped in the rx fifo (see section 123, rx fifo errored frame drop enable ($0x59f) can be optionally indicated with an rerr when sent out the spi3 interface. 0 = packets not indicated with rerr. 1 = packets indicated with rerr. r/w 0 table 147 spi3 receive configuration ($0x701) (continued) (sheet 3 of 3) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 210 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 8.4.10 serdes register overview table 149 through table 152, clock and interface mode change enable ports 0 - 3 ($0x794) , on page 211 define the contents of the serdes registers at base location 0x780, which contain the control and status for the four serdes interfaces on the ixf1104 mac. table 148 address parity error packet drop counter ($0x70a) bit name description type 1 default register description: this register counts the number of packets dropped due to parity error detection during the address selection cycle. 0x00000000 31:8 reserved reserved ro 0x000000 7:0 address parity error packet drop counter this is an 8-bit counter that counts the number of packets dropped due to parity error detection during the address selection cycle. this gets cleared when read and saturates at 8?hff. there is only one counter for address parity drop as address will be used only in mphy mode of operation. the counter gets cleared once the register is read. r0x00 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 149 tx driver power level ports 0 - 3 ($0x784) bit name description type default register description: allows selection of various pr ogrammable drive strengths on each serdes port. refer to section 5.6.2.2, transmitter programmable driver-power levels , on page 103 . 0x0000dddd 31:16 reserved reserved ro 0x0000 15:12 drvpwr3[3:0] encoded input that sets power level for port 3 r/w 1101 11:8 drvpwr2[3:0] encoded input that sets power level for port 2 r/w 1101 7:4 drvpwr1[3:0] encoded input that sets power level for port 1 r/w 1101 3:0 drvpwr0[3:0] encoded input that sets power level for port 0 r/w 1101 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 150 tx and rx power-down ($0x787) bit name description type default register description: tx and rx power-down bits to allow per-port power-down of unused ports 0x00000000 31:14 reserved reserved ro 0x0000000 13:10 tpwrdwn[3:0] tx power-down for ports 3-0 (1 = power-down) r/w 0000 9:4 reserved reserved ro 0x00 3:0 rpwrdwn[3:0] rx power-down for ports 3-0 (1 = power-down) r/w 0000 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 211 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 151 rx signal detect level ports 0 - 3 ($0x793) bit name description type 1 default register description: this register shows the status of the rx input in relation to the level of the signal being received from the line. this register is meant for debug and test use. 0x00000000 31:4 reserved reserved ro 0x0000000 3:0 sigdet[3:0] signal detect for ports 0-3 0 = noise 1 = signal ro 0x0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 152 clock and interface mode change enable ports 0 - 3 ($0x794) (sheet 1 of 2) bit name description type 1 default register description: this register is used when a c hange to the operational mode or speed of the ixf1104 mac is required. this regist er ensures that when a change is made that the internal clocking of the ixf1104 mac is managed correctly and no unexpected effects of the operational or speed change are obser vable on the line interfaces. 0x00000000 31:4 reserved reserved ro 0x0000000 3 clock and interface mode change enable port 3 2 enables internal clock g enerator for port 3 to sample the mac if mode and rgmii speed ($ port_index + 0x10) and the interface mode ($0x501) . 0 = set to zero when changes are being made to the mac if mode and rgmii speed ($ port_index + 0x10) and the interface mode ($0x501) . 1 = set to 1 for the configuration changes to take effect. r/w 0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write 2. refer to section 6.1, change port mode initialization sequence , on page 127 for the proper sequence to change the port mode and speed in conjunction with this register. page 212 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 8.4.11 optical module register overview table 153 through table 156, i 2 c data ports 0 - 3 ($0x79f) , on page 214 provide an overview of the optical module registers. note: all registers in this section are only applicable to ports that are configured in fiber mode. 2 clock and interface mode change enable port 2 2 enables internal clock g enerator for port 2 to sample the mac if mode and rgmii speed ($ port_index + 0x10) and the interface mode ($0x501) . 0 = set to zero when changes are being made to the mac if mode and rgmii speed ($ port_index + 0x10) and the interface mode ($0x501) . 1 = set to 1 for the configuration changes to take effect. r/w 0 1 clock and interface mode change enable port 1 2 enables internal clock g enerator for port 1 to sample the mac if mode and rgmii speed ($ port_index + 0x10) and the interface mode ($0x501) . 0 = set to zero when changes are being made to the mac if mode and rgmii speed ($ port_index + 0x10) and the interface mode ($0x501) . 1 = set to 1 for the configuration changes to take effect. r/w 0 0 clock and interface mode change enable port 0 2 enables internal clock g enerator for port 0 to sample the mac if mode and rgmii speed ($ port_index + 0x10) and the interface mode ($0x501) . 0 = set to zero when changes are being made to the mac if mode and rgmii speed ($ port_index + 0x10) and the interface mode ($0x501) . 1 = set to 1 for the configuration changes to take effect. r/w 0 table 152 clock and interface mode change enable ports 0 - 3 ($0x794) (sheet 2 of 2) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write 2. refer to section 6.1, change port mode initialization sequence , on page 127 for the proper sequence to change the port mode and speed in conjunction with this register. table 153 optical module status ports 0-3 ($0x799) (sheet 1 of 2) bit name description type 1 default register description: this register provides a means to control and monitor the interface to the optical modules when a port is used in fiber mode. 0x00000000 31:24 reserved reserved ro 0x00 23:20 rx_los_3:0 rx_los inputs for ports 0-3 r 0x0 19:14 reserved reserved 0x00 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 213 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 13:10 tx_fault_3:0 tx_fault inputs for ports 0-3 r 0x0 9:4 reserved reserved 0x00 3:0 mod_def_3:0 mod_def inputs for ports 0-3 r 0x0 table 153 optical module status ports 0-3 ($0x799) (continued) (sheet 2 of 2) bit name description type 1 default 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 154 optical module control ports 0 - 3 ($0x79a) bit name description type 1 default register description: this register provides access to optical module interrupt enables and sets the tx_disable output for the ports configured in fiber mode. 0x1e000 31:17 reserved reserved ro 0x0000 16:13 i 2 c_port_enable when set, individual ly enables the four i 2 c ports. r/w 0xf 12 rx_los_en enable for rx_los_int operation 1 = enabled r/w 0 11 tx_fault_en enable for tx_fault_int operation 1 = enabled r/w 0 10 mod_def_en enable for mod_def_int operation 1 = enabled r/w 0 9:4 reserved reserved ro 0x00 3:0 tx_disable_3:0 tx_disable outputs for ports 0-3 r/w 0x0 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 214 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 table 155 i 2 c control ports 0 - 3 ($0x79b) bit name description type 1 default register description: this register controls and monitors the interface to the optical modules when used in fiber mode. 0x00000000 31:29 reserved reserved ro 0x0 28 port address err (r) port addressing error. r 0 27 wp_err an attempt to write to the protected e 2 prom has occurred. r0 26 no_ack_err this bit is set to 1 when a write and subsequent read from an optical module interface has failed. this signal should be used to validate the data being read. data is only valid if this bit is equal to zero. r0 25 i 2 c_enable enable the i 2 c block. r/w 0 24 i 2 c_start start the i 2 c transfer. r/w 0 23 reserved reserved ro 0 22 write_complete bit is asserted when write access is complete. r 0 21 reserved reserved ro 0 20 read_complete bit asserted when read access is complete. r 0 19:18 reserved reserved ro 0 17:16 port select selects the port for which the i 2 c transaction is targeted. valid range is 0 to 3. r/w 00 15 read/write 0 = write transaction 1 = read transaction r/w 0 14:11 device id most-significant four bits of device address field. r/w 0x0 10:0 register address bits 10:8 select the least-significant three bits of the device address field bits 7:0 select the word/register address r/w 0x000 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write table 156 i 2 c data ports 0 - 3 ($0x79f) bit name description type 1 default register description: these registers hold data bytes that are read and written using the i 2 c interface to optical module interfaces connected to each port of the cortina systems ? ixf1104 4-port gigabit ethernet media access controller. 0x00000000 31:24 reserved reserved ro 0x00 23:16 write data bit 23=msb, bit 16 = lsb data to be written to the optical module interface. r/w 0x00 15:8 reserved reserved ro 0x00 7:0 read data bit 7 = msb, bit 0 = lsb data read from the optical module interface. r/w 0x00 1. ro = read only, no clear on read; r = read, clear on read; w = write only; r/w = read/write, no clear; r/w/c = read/write, clear on write page 215 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 page 216 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 9.0 mechanical specifications the ixf1104 mac is packaged in a 576-ball bga package with 6 balls removed diagonally from each corner, for a total of 5 52 balls used measuring 25 mm x 25 mm. the pitch of the package balls is 1 mm. 9.1 overview cbga (standard and rohs-compliant) and fc-pbga packages are suited for applications requiring high i/o counts and high electrical performance, and are recommended for high-power applications with high noise immunity requirements. note: the fc-pbga package will not be available un til mid-2006. please see your field sales representative for more detailed information. 9.1.1 features ? flip chip die attach; surface mount second-level interconnect ? high electrical performance ? high i/o counts ? area array i/o options ? multiple power-zone offering supports core and four additional voltages ? jedec-compliant package 9.2 package specifics the ixf1104 mac uses the following package: ? 576-ball bga package with 6 balls removed diagonally from each corner, for a total of 552 balls used ? ball pitch of 1.0 mm ? overall package dimensions of 25 mm x 25 mm page 217 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 9.3 package information 9.3.1 cbga package diagrams figure 54 and figure 55 illustrate the cbga top, bo ttom, and side package views. figure 54 cbga package diagram b0034-01 3.902 3.938 chip substrate 7.804 7.877 (25 0.2) (25 0.2) 47p6802 note: all dimensions are in mm. b0035-03 (25 0.2) (23) (25 0.2) (23) (23x) typ chip carrier a01 corner (23x) typ (0.825 max) (0.325 min) (reference) (0.825 max) (0.325 min) (575x) ( ? 0.8 0.05) (i/o pads) (reference) ? 0.20 da l s b s note: all dimensions are in mm. = ball = no ball page 218 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 9.3.2 flip chip-plastic ball grid array package diagram figure 56 illustrates the fc-pbga top a nd bottom package views and figure 57 lists the fc-pbga mechanical specifications. note: please contact your field sales representat ive for more information on the fc-pbga package. figure 55 cbga package side view diagram b0555-01 seating plane 0.15 c (4.237 max) (3.619 min) (3.327 max) (2.809 min) (0.857 max) (0.779 min) (4.16 max) (3.43 min) (6x) (3.24 max) (2.72 min) (6x) (2.47 max) (2.03 min) 0.81 0.1 (0.77 max) (0.69 min) (6x) chip c4 encapsulant fillet 45l4867 (552) solder ball note: all dimensions are in mm. page 219 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 figure 56 fc-pbga packag e (top and bottom views) b5181-02 basic 1.00 mm basic 1.00 mm ? eee (0.25) ? b (0.55 min 0.75 max) 01 terminal a01 identifier lid seating plane substrate abc 02 03 ca m b ? fff (0.10) c m e a e d e = no ball = ball notes: all dimensions are in millimeters. legend: top view bottom view c aaa (0.20) ccc (0.35) // c a (3.27 max) a1 (0.40 min) bbb (0.25) // c 25.0 nom ? 0.2 25.0 nom ? 0.2 all around ddd (0.20) b page 220 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 9.3.3 top label marking example figure 58 and figure 59 show example marking labels. note: in contrast to the pb-free (rohs-compliant ) package, the non-rohs-compliant package does not have the ?e1? symbol. figure 57 fc-pbga mechanical specifications page 221 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 figure 58 package marking example ? cortina systems marking aaaoooaaa aywwx00a country of origin device name fpo traceability code note: this is a generic example. markings for specific devices will vary. figure 59 package marking example ? intel* marking character font size 0.04 - 0.10? 0.06 - 0.10? 25.0 mm 7.5 x 7.5 mm 25.0 mm pin 1 mark a aa000aaa = intel product number 0.19 - 0.24? ? 0.07 - 0.12? r note: * "pin 1 " does mean a pin1 indicator, not an actual mark. country xx = intel silicon revision number, a0, a1, b0 ? note: diameter of trademark circles are 70 mils. height of circles surrounding pb-redced symbol are equal to overall character height substrate pn = substrate material number (barely visible) jjjjjjjj = manufacturin g lot number syww9001 = intel finished process order (fpo) numbe r country = assy plant country of ori g in topside fields not to scale diameter of pin 1 mark is 70 mils, and is located opposite the top-side substrate ?pin 1? identifier. qq = quality level, p: proto type, pq: potential qual?able, ? ?: production (no marking) ++ ++ = rework indicator syww9001 back of the die (bare silicon) substrate pn e 1 e 1 = pb-reduced indicator (same as jedec) b5131-01 note: the actual product name marking is ixf1 104ce, not hfixf1104ce (leaded version) and wfixf1104ce (pb-reduced), due to li dless package space limitation. page 222 cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 10.0 product ordering information table 157 and figure 60 provide ixf1104 mac product ordering information. table 157 product information product number revision package type rohs- compliant hfixf1104ce.b0 b0 cbga no wfixf1104ce.b0 b0 cbga yes hpixf1104be.b0 1 b0 pbga no note: 1. please contact your field sa les representative for detailed information on the fc-pbga package. figure 60 ordering information ? sample hf e 1104 c ixf b0 product revision xn = 2 alphanumeric characters temperature range a = ambient (0 ? 55 0 c) c = commercial (0 ? 70 0 c) e = extended (-40 ? 85 0 c) internal package designator l = lqfp p = plcc n = dip q = pqfp h = qfp t = tqfp b = bga c = cbga e = tbga k = hsbga (bga with heat slug product code xxxxx = 3-5 digit alphanumeric ixa product prefix lxt = phy layer device ixe = switching engine ixf = formatting device (mac/framer) ixp = network processor package designator b5118-04 page 223 end of document cortina systems ? ixf1104 4-port gigabit ethernet media access controller ixf1104 mac datasheet 278757, revision 10.0 29 november 2006 contact information contact information cortina systems, inc. 840 w. california ave sunnyvale, ca 94086 408-481-2300 sales@cortina-systems.com www.cortina-systems.com this document contains information proprietary to cortina syst ems, inc. any use or disclosure, in whole or in part, of this information to any unauthorized party, for any purposes other than that for which it is provided is expressly prohibited except as authorized by cortina systems, inc. in writing. cortina systems, inc. reserves its rights to pursue both civil and criminal penalties for copying or di sclosure of this material without authorization. *other names and brands may be clai med as the property of others. ? cortina systems, inc. 2006 |
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